Diodes Inc

The PI6CB332001 is a 20-output very low power PCIe® Gen 1/Gen 2/Gen 3/Gen 4/Gen 5 and Gen 6 clock buffer. It is capable of distributing the reference clocks for UPI, SAS, SATA, and other applications as well. It takes a reference input to fanout twenty 100MHz low power differential HCSL outputs with on-chip terminations. The on-chip termination can save 80 external resistors and make layout easier. OE pins combined with SMBus bits as well as 3-wire side band interface provide easier power management for each output.

The PI6CB332001A is a 20-output, very low-power, PCIe® 1.0/2.0/3.0/4.0/5.0/6.0 clock buffer. The device is capable of distributing the reference clocks for UPI, SAS, SATA, and other applications. It takes a reference input to fanout twenty 100MHz low-power differential HCSL outputs with on-chip terminations. The on-chip termination can save 80 external resistors and make layout easier. OE pins combined with SMBus bits, as well as a 3-wire side band interface, provide easier power management for each output. All OE pins are power down tolerant, which allows the OE pins to be driven by external signals when the device is in a power down or reset condition. The device must reset and power up properly if these pins are driven to any valid voltage prior to the assertion of VDD or PWRGD#.

The PI6CB33202 is a two-output very-low-power PCIe Gen1/ Gen2/Gen3/Gen4/Gen5 clock buffer. It takes a reference input tofan out two 100MHz low-power differential HCSL outputs with on-chip terminations. The on-chip termination can save eightexternal resistors and make layout easier. Individual OE pin for each output provides easier power management.

The PI6CB33401 is a 4-output very low power PCIe® Gen 1/Gen 2/Gen 3/Gen 4/Gen 5 clock buffer. It takes a reference input to fanout four 100MHz low power differential HCSL outputs with on-chip terminations. The on-chip termination can save 16 external resistors and make layout easier. Individual OE pin for each output provides easier power management.

The PI6CB33402 is a 4-output very low power PCIe® Gen 1/Gen 2/Gen 3/Gen 4/Gen 5 clock buffer. It takes a reference input to fanout four 100MHz low power differential HCSL outputs with on-chip terminations. The on-chip termination can save 16 external resistors and make layout easier. Individual OE pin for each output provides easier power management.

The PI6CB33602 is a 6-output very low power PCIe Gen1/Gen2/ Gen3/Gen4/Gen5 clock buffer. It takes a reference input to fanout six 100MHz low power differential HCSL outputs with on-chip terminations. The on-chip termination can save 24 external resistors and make layout easier. Individual OE pin for each output provides easier power management.

The PI6CB33801 is an eight-output very-low-power PCIe Gen1/ Gen2/Gen3/Gen4/Gen5 clock buffer. It takes a reference input to fanout eight 100MHz low-power differential HCSL outputs with on-chip terminations. The on-chip termination can save 32 external resistors and make layout easier. Individual OE pin for each output provides easier power management.

The PI6CB33802 is an eight-output very-low-power PCIe PCIe Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer. It takes a referenceinput to fanout eight 100MHz low-power differential HCSL outputs with on-chip terminations. The on-chip termination can save 32 external resistors and make layout easier. An individual OE pin for each output provides easier power management.

The PI6CBE33045 is a low-power PCIe® 1.0/2.0/3.0/ 4.0/5.0/6.0 clock buffer. It takes a reference input to fanout four 100MHz low-power differential HCSL outputs with on-chip terminations for 85Ω output impedance. It supports both zero-delay and fanout buffer functions for various applications. An individual OE pin for each output provides easier power management.

The DIODES PI6CBE33083 is a low-power PCIe® 1.0/2.0/3.0/ 4.0/5.0/6.0 clock buffer. It takes a reference input to fanout eight 100MHz low-power differential HCSL outputs with on-chip terminations for 33Ω output impedance. It supports both zero-delay and fanout buffer functions for various applications. An individual OE pin for each output provides easier power management. It uses Diodes proprietary PLL design to achieve very-low jitter that meets PCIe 1.0/2.0/3.0/4.0/5.0/6.0 requirements. Other than PCIe 100MHz support, this device also supports 133.33MHz via a pin.