Analog Devices

TheADSP-21062andADSP-21060SHARC DSPs are signal processing microcomputers that offer new capabilities and levels of performance. The ADSP-2106x SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.The ADSP-2106x SHARC DSP represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including a 4 Mbit SRAM memory (2 Mbit on the ADSP-21062, 1 Mbit on the ADSP-21061), host processor interface, DMA controller, serial ports, and link port and parallel bus connectivity for glueless DSP multiprocessing.

The ADSP-21065L is a general purpose, programmable 32-bit DSP that allows users to program with equal efficiency in both fixed-point or floating-point arithmetic. This programming flexibility combined with the high performance core and integrated peripherals make the ADSP-21065L an outstanding price/performance value for a broad base of consumer, communications, automotive, industrial and computer applications.The ADSP-21065L is code compatible with ADI's SHARC DSP family and as such customers have immediate access to software and hardware development tools from ADI and SHARC third parties.

The ADSP-21161 SHARC®DSP is the newest member of the Super Harvard Architecture (SHARC) family of programmable DSPs. Capable of 600 million math operations per second (MFLOPs), the ADSP-21161 sets a new level of performance for low-cost SHARC DSPs - more than three times the performance for comparable models at about the same price. Its road map includes a cost-effective path to 1200 MFLOPS for $5 per unit and a performance-driven path to 10 GFLOPS and beyond."This newest edition to the SHARC family will open more possibilities for designers to design-in high performance digital signal processing into client-side applications and should help others reconsider applications they couldn’t do before with a single chip," said Will Strauss, president of Forward Concepts. "Analog Devices will certainly maintain customer loyalty with this road map."The ADSP-21161 DSP is the second member of the SHARC DSP family of 32-bit floating-point programmable DSPs to be based on a SIMD core architecture that is optimized for digital signal processing performance. Like all SHARCs, the ADSP-21161 is code-compatible with all other members of the family and supports both fixed- and floating-point data types. The ADSP-21161 lowers the price for SIMD SHARC DSP performance and is an outstanding DSP solution for many price-sensitive applications.State-of-the-Art Development ToolsThe ADSP-21161, like all SHARC processors, is supported by a complete set of software and hardware development tools. The VisualDSP++®tool set offered by Analog Devices includes an optimizing C/C++ compiler, integrated development environment (IDE), assembler, linker, splitter and cycle accurate simulator that support both C and assembly debugging. Emulation support is JTAG-based and ADI offers USB, PCI, and Ethernet based emulators.SHARC DSP RoadmapThere are two code-compatible paths that the SHARC DSP roadmap will follow. One optimized for high-performance multiprocessing systems and the other for price/performance. Performance is the key for multiprocessing applications and this is the reason that ADI will offer 10 GFLOP SHARC DSPs in the future. On-chip memory sizes will be balanced to match this performance with memories increasing to unprecedented levels (64 Mbit) using newly developed technologies.Industry leading price/performance will be the driver on the other path of the roadmap. In the future, these SHARC DSPs will offer an increase in performance to 1200 MFLOPs while decreasing price to as low as $5.00. This is required to support new technologies that demand substantial signal processing performance at consumer price points.

The ADSP-21261 is the lowest cost member of the third-generation of SHARC®programmable digital signal processors. A range of cost-sensitive applications such as voice recognition, medical appliances, measurement devices, high-quality audio, and automotive entertainment systems will benefit from the ADSP-21261’s integration of large on-chip memory and diverse set of peripherals.The ADSP-21261 is well suited for use in cost sensitive, signal processing applications.The ADSP-21261 is based on the SHARC (SIMD) core that supports execution of 32-bit fixed-point and 32/40-bit floating-point arithmetic formats. With its core running at 150MHz (6.67 ns instruction cycle time), the ADSP-21261 is capable of executing complex Fast Fourier Transform (FFT) operations—1024-point complex FFT in 61us. The processor’s single-instruction, multiple data (SIMD) mode effectively doubles the processor performance.The ADSP-21261 offers a high level of integration, including 1 Mbit of on-chip dual-ported SRAM and 3Mbits of mask programmable ROM memory. This large on-chip dual-ported memory enables sustained processor and I/O performance without the need for external memory. System I/O is achieved through four full-duplex serial ports, four timers, a 16-bit parallel port, a serial peripheral interface (SPI), 18 zero-overhead Direct Memory Access (DMA) channels delivering fast data transfers without processor intervention and an innovative Digital Audio Interface (DAI) which provides the user complete software control through its Signal Routing Unit (SRU).Digital Audio Interface (DAI) for Simplified I/O System DevelopmentThe ADSP-21261 utilizes the Digital Audio Interface (DAI), an architecture that enables complete software programmability of various on-chip peripherals. The flexibility and ease-of-use of the SHARC programming model, combined with the DAI, allow manufacturers to deploy one hardware configuration into multiple product offerings with different I/O requirements.Connections are made using the flexible Signal Routing Unit (SRU), a matrix routing group of pins that provides configurable and flexible connectivity between all DAI components and the SRU. The peripherals connected through the DAI are: a precision clock generator (PCG), an input data port (IDP), four SPORTS (serial ports), six flag inputs, six flag outputs, three timers and the SRU. The IDP provides an additional input path to the DSP core, configurable as 8 channels of receive serial data or as 7 channels of receive serial data and a single channel of up to a 20-bit wide parallel data. This level of integration enables the designer to take full advantage of a wide variety of peripherals without sacrificing the overall system performance.CROSSCORE Development ToolsAll 3rd Generation SHARC Processors are supported by ADI’s CROSSCORE brand of award winning development tools. The CROSSCORE components include the VisualDSP++™software development environment, EZ-KIT Lite™evaluation systems, and emulators.VisualDSP++ is an integrated software development environment, allowing for fast and easy development, debug, and deployment. The EZ-KIT Lite evaluation system provides an easy way to investigate the power of the ADI family of processors and begin to develop applications. Emulators are available for PCI and USB host platforms for rapid on-chip debugging. Additional development tools and algorithms are available from an extensive third-party development community.Note: The functional block diagram is available in the data sheet.