Analog Devices

The ADN2815 provides the receiver functions of quantization and clock and data recovery for continuous data rates from 10 Mb/s to 1.25 Gb/s. The ADN2815 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.The ADN2815 is available in a compact 5 mm × 5 mm 32-lead LFCSP.ApplicationsSONET OC-1/-3/-12 and all associated FEC ratesFibre Channel, GbE, HDTVsWDM transpondersRegenerators/repeatersTest equipmentBroadband crossconnects and routers

The ADN2816 provides the receiver functions of quantization and clock and data recovery for continuous data rates from 10 Mb/s to 675 Mb/s. The ADN2816 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.The ADN2816 is available in a compact 5 mm × 5 mm 32-lead chip scale package.ApplicationsSONET OC-1/3/12 and all associated FEC ratesFibre Channel, ESCON, Fast Ethernet, SDI, etc.WDM transpondersRegenerators/repeatersTest equipmentBroadband cross-connects and routers

The ADN2817/ADN2818provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ ADN2818 automatically lock to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver.The ADN2817/ADN2818 have many optional features available through an I2C interface. For example, the user can read back the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. A BERMON circuit provides an estimate of the received bit error rate (BER) without interruption of the data. Alternatively, the user can adjust the data sampling phase to optimize the received BER.The ADN2817/ADN2818 are available in a compact 5 mm × 5 mm, 32-lead, lead frame chip scale package.ApplicationsSONET OC-1, OC-3, OC-12, OC-48, and all associated FEC ratesFibre Channel, 2× Fibre Channel, GbE, HDTV, and othersWDM transpondersRegenerators/repeatersTest equipmentData Sheet, Rev. A, 8/08

The ADN2819 provides receiver functions of Quantization, Signal Level Detect and Clock and Data Recovery at rates of OC-3, OC-12, Gigabit Ethernet, OC-48 and all FEC rates. All SONET jitter requirements are met, including: Jitter Transfer; Jitter Generation; and Jitter Tolerance. All specifications are quoted for-40ºCto +85ºC ambient temperature unless otherwise noted.The proprietary delay and phase-locked loop design of the ADN2819 provides unprecedented jitter performance for robust high-speed networking designs.The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip crystal oscillator. Both native rates and 15/14 rate digital wrappers rates are supported by the ADN2819, without any change of reference clock required. This device together with a PIN diode and a TIA preamplifier can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end Signal Detect circuit indicates when the input signal level has fallen below a user adjustable threshold.

The ADN2855 is a burst mode clock and data recovery IC designed for GPON/BPON/GEPON optical line terminal (OLT) receiver applications. The part can operate at 155.52 Mbps, 622.08 Mbps, 1244.16 Mbps, or 1250.00 Mbps data rates, selectable via the I2C interface.The ADN2855 frequency locks to the OLT reference clock and aligns to the input data within 12 bits of the start of the preamble. The device provides a full rate or an optional half rate output clock for a double data rate (DDR) interface to an FPGA or digital ASIC.All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. The ADN2855 is available in a compact 5 mm × 5 mm, 32-lead chip scale package.ApplicationsPassive optical networksGPON/BPON/GEPON OLT receivers