Analog Devices

The AD9981 is a complete, 10-bit, 95 MSPS, monolithic analog interface optimized for capturing YPbPr video and RGB graphics signals. Its 95 MSPS encode rate capability and full-power analog bandwidth of 200 MHz supports all HDTV video modes and graphics resolutions up to XGA (1024 × 768 at 85 Hz).The AD9981 includes a 95 MHz triple ADC with an internal reference, a PLL, programmable gain, offset, and clamp controls. The user provides only 3.3 V and 1.8 V power supplies and an analog input. Three-state CMOS outputs may be powered from 1.8 V to 3.3 V.The AD9981’s on-chip PLL generates a sample clock from the three-level sync (for YPbPr video) or the horizontal sync (for RGB graphics). Sample clock output frequencies range from 10 MHz to 95 MHz. PLL clock jitter is 9% or less p-p typical at 95 MSPS.With internal coast generation, the PLL maintains its output frequency in the absence of sync input. A 32-step sampling clock phase adjustment is provided. Output data, sync, and clock phase relationships are maintained.The auto-offset feature can be enabled to automatically restore the signal reference levels and to automatically calibrate out any offset differences between the three channels. The AD9981 also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin.Fabricated in an advanced CMOS process, the AD9981 is provided in a space-saving, 80-pin, Pb-free, LQFP surface mount plastic package. It is specified over the 0°C to +70°C temperature range.APPLICATIONSAdvanced TVsPlasma display panelsLCDTVHDTVRGB graphics processingLCD monitors and projectorsScan converters

The AD9984A is a complete 10-bit, 170 MSPS, monolithic analog interface optimized for capturing YPbPr video and RGB graphics signals. Its 170 MSPS encode rate capability and full power analog bandwidth of 300 MHz support all HDTV video modes up to 1080p, as well as graphics resolutions up to UXGA (1600 × 1200 at 60 Hz).The AD9984A includes a 170 MHz triple ADC with an internal reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 1.8 V power supply and an analog input. Three-state CMOS outputs can be powered from 1.8 V to 3.3 V.The AD9984A on-chip PLL generates a sample clock from the tri-level sync (for YPbPr video) or the horizontal sync (for RGB graphics). Sample clock output frequencies range from 10 MHz to 170 MHz. With internal coast generation, the PLL maintains its output frequency in the absence of a sync input. A 32-step sampling clock phase adjustment is provided. Output data, sync, and clock phase relationships are maintained.The auto-offset feature can be enabled to automatically restore the signal reference levels and calibrate out any offset differences between the three channels. The auto channel-to-channel gain-matching feature can be enabled to minimize any gain mismatches between the three channels.The AD9984A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or can be provided by the user through the CLAMP input pin.Fabricated in an advanced CMOS process, the AD9984A is provided in a space-saving, Pb-free, 80-lead low profile quad flat package (LQFP) or 64-lead lead frame chip scale package (LFCSP) and is specified over the 0°C to 70°C temperature range.APPLICATIONSAdvanced TVsPlasma display panelsLCDTVHDTVRGB graphics processingLCD monitors and projectorsScan converters

The AD9985A is a complete 8-bit, 140 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz support resolutions up to SXGA (1280 × 1024 at 75 Hz).The AD9985A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and horizontal sync (Hsync) and Coast signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.The AD9985A’s on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync, and clock output phase relationships are maintained.The AD9985 also offers full sync processing for composite sync and sync-on-green applications, variable analog input bandwidth control, variable SOGIN bandwidth control and selectable input filtering.A clamp signal is generated internally or can be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface.Fabricated in an advanced CMOS process, the AD9985A is provided in a space-saving 80-lead LQFP surface-mount Pb-free plastic package, and is specified over the –40°C to +85°C temperature range.APPLICATIONSRGB graphics processingLCD monitors and projectorsPlasma display panelsScan convertersMicrodisplaysDigital TVs

The AD9986 is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate RF DAC core, and a 12-bit, 6 GSPS rate RF ADC core. The AD9986 supports four transmitter channels and two receiver channels with four transmitter, two receiver (4T2R) configuration. The AD9986 is well suited for 2-antenna and 4-antenna transmitter applications requiring a wide bandwidth observation receiver path for the digital predistortion. The AD9986 supports up to a 6 GSPS complex transmit and receive data rate in single channel mode. The maximum radio channel bandwidth supported is 1.2 GHz and 2.4 GHz for the transmit and receive paths, respectively (4T2R). The AD9986 features a 16 lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B serial data port, an on-chip clock multiplier, and digital signal processing capability targeted at multiband, direct-to-RF radio applications.APPLICATIONSWireless communications infrastructureW-CDMA, LTE, LTE-A, Massive-MIMOMicrowave point-to-point, E-band, and 5G mm WaveBroadband communications systemsDOCSIS 3.1 and 4.0 CMTSCommunications test and measurement system

The AD9992 is a highly integrated CCD signal processor for digital still camera applications. It includes a complete analog front end with analog to digital conversion combined with a full-function programmable timing generator. The timing generator is capable of supporting up to 24 vertical clock signals to control advanced CCDs. APrecision Timing™ core allows adjustment of high speed clocks with approximately 400 ps resolution at 40 MHz operation. The AD9992 also contains eight general-purpose inputs/outputs that can be used for shutter and system functions.The AD9992 is specified at pixel rates of up to 40 MHz. The analog front end includes black level clamping, CDS, VGA, and a 12-bit analog-to-digital converter (ADC). The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. Operation is programmed using a 3-wire serial interface.The AD9992 is specified over an operating temperature range of −25°C to +85°C.ApplicationsDigital still cameras