Analog Devices

The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with two internal high speed, high performance quadrature DACs to form a digitally programmable I and Q synthesizer function. When referenced to an accurate clock source, the AD9854 generates highly stable, frequency-phase, amplitude-programmable sine and cosine outputs that can be used as an agile LO in communications, radar, and many other applications. The innovative high speed DDS core of the AD9854 provides 48-bit frequency resolution (1 μHz tuning resolution with 300 MHz SYSCLK). Retaining 16 bits for phase-to-amplitude conversion ensures excellent spurious-free dynamic range (SFDR).The circuit architecture of the AD9854 allows the generation of simultaneous quadrature output signals at frequencies up to 150 MHz, which can be digitally tuned at a rate of up to 100 million new frequencies per second. The sine wave output (externally filtered) can be converted to a square wave by the internal comparator for agile clock generator applications. The device provides two 14-bit phase registers and a single pin for BPSK operation.For higher-order PSK operation, the I/O interface can be used for phase changes. The 12-bit I and Q DACs, coupled with the innovative DDS architecture, provide excellent wideband and narrow-band output SFDR. The Q DAC can also be configured as a user-programmable control DAC if the quadrature function is not desired. When configured with the comparator, the 12-bit control DAC facilitates static duty cycle control in high speed clock generator applications.Two 12-bit digital multipliers permit programmable amplitude modulation, on/off output shaped keying, and precise amplitude control of the quadrature output. Chirp functionality is also included to facilitate wide bandwidth frequency sweeping applications. The programmable 4× to 20× REFCLK multiplier circuit of the AD9854 internally generates the 300 MHz system clock from an external lower frequency reference clock. This saves the user the expense and difficulty of implementing a 300 MHz system clock source.Direct 300 MHz clocking is also accommodated with either single-ended or differential inputs. Single-pin conventional FSK and the enhanced spectral qualities of ramped FSK are supported. The AD9854 uses advanced 0.35 µm CMOS technology to provide a high level of functionality on a single 3.3 V supply.The AD9854 is pin-for-pin compatible with the AD9852 single-tone synthesizer. It is specified to operate over the extended industrial temperature range of −40°C to +85°C.ApplicationsAgile, quadrature LO frequency synthesisProgrammable clock generatorsFM chirp source for radar and scanning systemsTest and measurement equipmentCommercial and amateur RF exciters

The AD9857 integrates a high speed direct digital synthesizer (DDS), a high performance, high speed, 14-bit digital-to-analog converter (DAC), clock multiplier circuitry, digital filters, and other DSP functions onto a single chip, to form a complete quadrature digital upconverter device. The AD9857 is intended to function as a universal I/Q modulator and agile upconverter, single-tone DDS, or interpolating DAC for communications applications, where cost, size, power dissipation, and dynamic performance are critical attributes.The AD9857 offers enhanced performance over the industry-standard AD9856, as well as providing additional features.The AD9857 is available in a space-saving, surface-mount package and is specified to operate over the extended industrial temperature range of −40°C to +85°C.APPLICATIONSHFC data, telephony, and video modemsWireless base stationAgile, LO frequency synthesisBroadband communications

The AD9861 is a member of the MxFE family—a group of integrated converters for the communications market. The AD9861 integrates dual 10-bit analog-to-digital converters (ADC) and dual 10-bit digital-to-analog converters (TxDAC®). Two speed grades are available, -50 and -80. The -50 is optimized for ADC sampling of 50 MSPS and less, while the -80 is optimized for ADC sample rates between 50 MSPS and 80 MSPS. The dual TxDACs operate at speeds up to 200 MHz and include a bypassable 2× or 4× interpolation filter. Three auxiliary converters are also available to provide required system level control voltages or to monitor system signals. The AD9861 is optimized for high performance, low power, small form factor, and to provide a cost-effective solution for the broadband communication market.The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADC and TxDAC clocks are generated within a timing generation block that provides user programmable options such as divide circuits, PLL multipliers, and switches.A flexible, bidirectional 20-bit I/O bus accommodates a variety of custom digital back ends or open market DSPs.In half-duplex systems, the interface supports 20-bit parallel transfers or 10-bit interleaved transfers. In full-duplex systems, the interface supports an interleaved 10-bit ADC bus and an interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin count and, therefore, reduces the required package size on the AD9861 and the device to which it connects.The AD9861 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC interpolation rate, and control ADC and TxDAC power-down. The SPI provides more programmable options for both the TxDAC path (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal duty cycle stabilizer, and twos complement data format).The AD9861 is packaged in a 64-lead LFCSP (low profile, fine pitched, chip scale package). The 64-lead LFCSP footprint is only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into tightly spaced applications such as PCMCIA cards.ApplicationsBroadband accessBroadband LANCommunications (modems)

TheAD9860/ AD9862 are versatile integrated mixed signal front ends that are optimized for broadband wireless applications. The AD9860 / AD9862 are cost effective high performance mixed signal solutions for standards based or proprietary fixed access, modem, or wireless networking applications where dynamic performance, power dissipation, cost, and size are critical attributes.The AD9860 / AD9862 receive path includes dual high-performance, 10-/12-bit, 64 MSPS analog to digital converters, with input buffers, programmable gain amplifiers, and decimation filters. The transmit path contains dual high-performance 12-/14-bit 128 MSPS digital-to-analog converters, programmable gain amplifiers, interpolation filters, a digital Hilbert filter, and digital mixers for complex or real signal up-conversion.APPLICATIONSBroadband wireless...MMDS, IEEE 802.16Wireless LAN...IEEE 802.11Wideband cellular...Wideband CDMA, 3G, 4G cellularBroadband modems...Residential gateways, Power-line networking

The AD9865 is a mixed-signal front end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 80 MSPS. Its flexible digital interface, power saving modes, and high Tx-to-Rx isolation make it well suited for half- and full-duplex applications. The digital interface is extremely flexible allowing simple interfaces to digital back ends that support half- or full-duplex data transfers, thus often allowing the AD9865 to replace discrete ADC and DAC solutions. Power saving modes include the ability to reduce power consumption of individual functional blocks, or to power down unused blocks in half-duplex applications. A serial port interface (SPI®) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks from a single crystal or clock source.The Tx signal path consists of a bypassable 2×/4× low-pass interpolation filter, a 10-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate of 80 MSPS. The TxDAC provides differential current outputs that can be steered directly to an external load or to an internal low distortion current amplifier. The current amplifier (IAMP) can be configured as a current- or voltage-mode line driver (with two external npn transistors) capable of delivering in excess of 23 dBm peak signal power. Tx power can be digitally controlled over a 19.5 dB range in 0.5 dB steps.The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. The low noise RxPGA has a programmable gain range of −12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3 nV/rtHz for gain settings beyond 36 dB. The receive path LPF cutoff frequency can be set over a 15 MHz to 35 MHz range or simply bypassed. The 10-bit ADC achieves excellent dynamic performance over a 5 MSPS to 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization.The AD9865 provides a highly integrated solution for many broadband modems. It is available in a space saving 64-pin chip scale package and is specified over the commercial (−40°C to +85°C) temperature range.ApplicationsPowerline networkingVDSL and HPNA

The AD9874 is a general purpose IF subsystem that digitizes a low level 10-300MHz IF input signal with a bandwidth of up to 270 kHz. The signal chain of the AD9874 contains a low-noise amplifier, mixer, a band pass sigma-delta analog-to-digital converter and a decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit provides the AD9874 with 12 dB of continuous gain adjustment.The high dynamic range and inherent anti-aliasing provided by the bandpass sigma delta converter allows the AD9874 to cope with blocking signals 95 dB stronger than the desired signal. Auxiliary blocks include clock and LO synthesizers in addition to a serial peripheral interface port.The SPI port programs numerous parameters of the AD9874, thus allowing the device to be optimized for any given application. Programmable parameters include synthesizer divide ratios, AGC attenuation and attack/decay time, received signal strength level, decimation factor, output data format, 16 dB attenuator, and the selected bias currents. The bias currents of the LNA and mixer can be further reduced at the expense of degraded performance for battery-powered applications.APPLICATIONSMultimode Narrow-Band Radio Products- Analog/Digital UHF/VHF FDMA Receivers- TETRA, APCO25, GSM/EDGEPortable and Mobile Radio ProductsBase Station ApplicationsSATCOM Terminals