SN74AHC165-Q1 Series

Automotive 4.5-V to 5.5-V 8-bit parallel-load shift register

Catalog

Automotive 4.5-V to 5.5-V 8-bit parallel-load shift register

Part	Package / Case [x]	Package / Case	Package / Case [y]	Function	Number of Elements	Logic Type	Supplier Device Package	Grade	Output Type	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Qualification	Voltage - Supply [Max]	Voltage - Supply [Min]
Texas Instruments SN74AHC165QPWRQ1	0.173 in	16-TSSOP	4.4 mm	Parallel or Serial to Serial	1	Shift Register	16-TSSOP	Automotive	Complementary	8	125 °C	-40 °C	Surface Mount	AEC-Q100	5.5 V	2 V
Texas Instruments SN74AHC165QWBQBRQ1		16-WFQFN Exposed Pad		Parallel or Serial to Serial	1	Shift Register	16-WQFN (2.5x3.5)	Automotive	Complementary	8	125 °C	-40 °C	Surface Mount Wettable Flank	AEC-Q100	5.5 V	2 V

Catalog

Automotive 4.5-V to 5.5-V 8-bit parallel-load shift register

Key Features

• AEC-Q100 qualified for automotive applications:Device temperature grade 1: -40°C to +125°CDevice HBM ESD classification level 2Device CDM ESD classification level C4BAvailable in wettable flank QFN (WBQA) packageOperating range 2-V to 5.5-V V CCLow delay, 6 ns (25 °C, 5 V)Latch-up performance exceeds 250 mA per JESD 17AEC-Q100 qualified for automotive applications:Device temperature grade 1: -40°C to +125°CDevice HBM ESD classification level 2Device CDM ESD classification level C4BAvailable in wettable flank QFN (WBQA) packageOperating range 2-V to 5.5-V V CCLow delay, 6 ns (25 °C, 5 V)Latch-up performance exceeds 250 mA per JESD 17

Description

The SN74AHC165-Q1 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state. The SN74AHC165-Q1 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state.