LMK5B33414 Series

14-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO

Catalog

14-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO

Part	PLL	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Divider/Multiplier	Input	Supplier Device Package	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Frequency - Max [Max]	Number of Circuits	Output	Ratio - Input:Output [custom]	Differential - Input:Output [custom]	Differential - Input:Output [custom]
Texas Instruments LMK5B33414RGCT		Surface Mount	3.465 V	3.135 V	Yes/No	Crystal HCSL LVCMOS LVDS LVPECL	64-VQFN (9x9)	64-VFQFN Exposed Pad	85 °C	-40 °C	1.25 GHz 25 MHz 200 MHz 400 MHz	1	CML LVCMOS LVDS LVPECL	4:14
Texas Instruments LMK5B33414RGCR		Surface Mount	3.465 V	3.135 V	Yes/No	Crystal HCSL LVCMOS LVDS LVPECL	64-VQFN (9x9)	64-VFQFN Exposed Pad	85 °C	-40 °C	1.25 GHz 25 MHz 200 MHz 400 MHz	1	CML LVCMOS LVDS LVPECL	4:14

Catalog

14-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO

Key Features

• Ultra-low jitter BAW VCO based Ethernet clocks13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF)24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF42fs typical/ 60fs maximum RMS jitter at 312.5MHz47fs typical/ 65fs maximum RMS jitter at 156.25MHzThree high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)Programmable DPLL loop bandwidth from 1mHz to 4kHz< 1ppt DCO frequency adjustment step sizeFour differential or single-ended DPLL inputs1Hz (1PPS) to 800MHz input frequencyDigital holdover and hitless switching14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formatsUp to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N1Hz (1PPS) to 1250MHz output frequency with programmable swing and common modePCIe Gen 1 to 6 compliantI2C, 3-wire SPI, or 4-wire SPI–40°C to 85°C operating temperatureUltra-low jitter BAW VCO based Ethernet clocks13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF)24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF42fs typical/ 60fs maximum RMS jitter at 312.5MHz47fs typical/ 65fs maximum RMS jitter at 156.25MHzThree high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)Programmable DPLL loop bandwidth from 1mHz to 4kHz< 1ppt DCO frequency adjustment step sizeFour differential or single-ended DPLL inputs1Hz (1PPS) to 800MHz input frequencyDigital holdover and hitless switching14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formatsUp to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N1Hz (1PPS) to 1250MHz output frequency with programmable swing and common modePCIe Gen 1 to 6 compliantI2C, 3-wire SPI, or 4-wire SPI–40°C to 85°C operating temperature

Description

The LMK5B33414 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5ns timing accuracy (ITU-T G.8273.2 Class D). The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use. APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in the VCO and can generate 312.5MHz output clocks with 42fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 feature conventional LC VCOs to provide options for a second or third frequency and/or synchronization domain. Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs. The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options. The LMK5B33414 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5ns timing accuracy (ITU-T G.8273.2 Class D). The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use. APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in the VCO and can generate 312.5MHz output clocks with 42fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 feature conventional LC VCOs to provide options for a second or third frequency and/or synchronization domain. Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs. The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.