74HC175 Series

Quad D Flip-Flop with Common Clock and Reset

Catalog

Quad D Flip-Flop with Common Clock and Reset

Part	Type	Number of Bits per Element	Current - Quiescent (Iq)	Max Propagation Delay	Max CL	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Package Name	Clock Frequency	Function	Operating Temperature (Max)	Operating Temperature (Min)	Package Length	Package Width	Number of Elements	Current - Output High	Current - Output Low	Output Type	Mounting Type	Trigger Type	Input Capacitance
NXP USA Inc. 74HC175PW-Q100J	D-Type	4 bits	8 µA	30 ns	50 pF	2 V	6 V	16-TSSOP	89 MHz	Master Reset	125 °C	-40 °C	0.173 in	4.4 mm	1	5.2 mA	5.2 mA	Complementary	Surface Mount	Positive Edge	3.5 pF
NXP USA Inc. 74HC175DB,112	D-Type	4 bits	8 µA	30 ns	50 pF	2 V	6 V	16-SSOP	89 MHz	Master Reset	125 °C	-40 °C	0.209 in	5.3 mm	1	5.2 mA	5.2 mA	Complementary	Surface Mount	Positive Edge	3.5 pF

Catalog

Quad D Flip-Flop with Common Clock and Reset

Description

The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. Information at the D inputs of the MM74HC175 is transferred to the Q and Q# outputs on the positive going edge of the clock pulse. Both true and complement outputs from each flip flop are externally available. All four flip-flops are controlled by a common clock and a common CLEAR. Clearing is accomplished by a negative pulse at the CLEAR input. All four Q outputs are cleared to a logical "0" and all four Q# outputs to a logical "1." The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCCand ground.