ADC12DJ5200-EP Series

Enhanced-product 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

Catalog

Enhanced-product 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

Part	Input Type	Data Interface	Package / Case	Reference Type	Architecture	Sampling Rate (Per Second)	Number of Inputs	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Number of A/D Converters	Configuration	Number of Bits	Supplier Device Package	Mounting Type	Operating Temperature [Min]	Operating Temperature [Max]
Texas Instruments V62/22611-01XF	Differential Single Ended	JESD204B JESD204C	144-FBGA FCBGA	External Internal	Folding Interpolating	5.2 G 10.4 G	2 4	1.15 V	1.05 V	125 °C	-55 °C	1.05 V 1.8 V	1.15 V 2 V	2	S/H-MUX-ADC	12 bits	144-FCBGA (10x10)	Surface Mount
Texas Instruments ADC12DJ5200ALREP	Differential Single Ended	JESD204B JESD204C	144-FBGA FCBGA	External Internal	Folding Interpolating	5.2 G 10.4 G	2 4	1.15 V	1.05 V			1.05 V 1.8 V	1.15 V 2 V	2	S/H-MUX-ADC	12 bits	144-FCBGA (10x10)	Surface Mount	-55 °C	125 °C

Catalog

Enhanced-product 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

Key Features

• High reliability enhanced product:Controlled baseline: one assembly and test site, one fabrication site, extended product lifecycle, extended product-change notification and product traceabilityADC core:12-bit resolutionUp to 10.4GSPS in single-channel modeUp to 5.2GSPS in dual-channel modePerformance specifications:Noise floor (–20dBFS, VFS = 1VPP-DIFF):Dual-channel mode: –151.8dBFS/HzSingle-channel mode: –154.4dBFS/HzENOB (dual channel, FIN = 2.4GHz): 8.6 BitsBuffered analog inputs with VCMI of 0V:Analog input bandwidth (–3dB): 8GHzUsable input frequency range: > 10GHzFull-scale input voltage (VFS, default): 0.8VPPNoiseless aperture delay (tAD) adjustment:Precise sampling control: 19fs StepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTime stamp for sample markingJESD204C serial data interface:Maximum lane rate: 17.16GbpsSupport for 64b/66b and 8b/10b encoding8b/10b modes are JESD204B compatibleOptional digital down-converters (DDC):4x, 8x, 16x and 32x complex decimationFour independent 32-Bit NCOs per DDCPeak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)Programmable FIR filter for equalizationPower consumption: 4WPower supplies: 1.1V, 1.9VHigh reliability enhanced product:Controlled baseline: one assembly and test site, one fabrication site, extended product lifecycle, extended product-change notification and product traceabilityADC core:12-bit resolutionUp to 10.4GSPS in single-channel modeUp to 5.2GSPS in dual-channel modePerformance specifications:Noise floor (–20dBFS, VFS = 1VPP-DIFF):Dual-channel mode: –151.8dBFS/HzSingle-channel mode: –154.4dBFS/HzENOB (dual channel, FIN = 2.4GHz): 8.6 BitsBuffered analog inputs with VCMI of 0V:Analog input bandwidth (–3dB): 8GHzUsable input frequency range: > 10GHzFull-scale input voltage (VFS, default): 0.8VPPNoiseless aperture delay (tAD) adjustment:Precise sampling control: 19fs StepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTime stamp for sample markingJESD204C serial data interface:Maximum lane rate: 17.16GbpsSupport for 64b/66b and 8b/10b encoding8b/10b modes are JESD204B compatibleOptional digital down-converters (DDC):4x, 8x, 16x and 32x complex decimationFour independent 32-Bit NCOs per DDCPeak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)Programmable FIR filter for equalizationPower consumption: 4WPower supplies: 1.1V, 1.9V

Description

The ADC12DJ5200-EP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200-EP can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC12DJ5200-EP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers. Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization. The ADC12DJ5200-EP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200-EP can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC12DJ5200-EP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers. Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.