ADC12DL500 Series

12-bit, dual 500MSPS or single 1GSPS analog-to-digital converter (LVDS interface)

Catalog

12-bit, dual 500MSPS or single 1GSPS analog-to-digital converter (LVDS interface)

Part	Package / Case	Number of A/D Converters	Ratio - S/H:ADC	Reference Type	Number of Inputs	Input Type	Configuration	Number of Bits	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Supplier Device Package	Architecture	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Sampling Rate (Per Second)	Data Interface	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments ADC12DL500ACF	256-BBGA FCBGA	2	0:2	Internal	1 2	Differential Single Ended	MUX-ADC	12 bits	1.15 V	1.05 V	256-FCBGA (17x17)	Folding Interpolating	1.05 V 1.8 V	1.15 V 2 V	1 G	LVDS - Parallel	Surface Mount	85 °C	-40 °C

Catalog

12-bit, dual 500MSPS or single 1GSPS analog-to-digital converter (LVDS interface)

Key Features

• ADC core:12-Bit resolutionUp to 1GSPS, 3GSPS, 5GSPS in single-channel modeUp to 500MSPS, 1.5GSPS, 2.5GSPS in dual-channel modeInternal dither for low-magnitude, high-order harmonicsLow-latency LVDS interface:Total latency: < 10nsUp to 48 data pairs at 1.6GbpsFour DDR data clocksStrobe signals simplify synchronizationNoise floor (no input, VFS = 1VPP-DIFF):Dual-channel mode: -143.5, -148, -149.8dBFS/HzSingle-channel mode: -146.2, -150.3, -152.2dBFS/HzBuffered analog inputs with VCMI of 0V:Analog input bandwidth (–3dB): 8GHzFull-scale input voltage (VFS, default): 0.8VPPNoiseless aperture delay (TAD) adjustment:Precise sampling control: 19fs stepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTimestamp for sample markingPower consumption: 2.6, 2.8, 3WADC core:12-Bit resolutionUp to 1GSPS, 3GSPS, 5GSPS in single-channel modeUp to 500MSPS, 1.5GSPS, 2.5GSPS in dual-channel modeInternal dither for low-magnitude, high-order harmonicsLow-latency LVDS interface:Total latency: < 10nsUp to 48 data pairs at 1.6GbpsFour DDR data clocksStrobe signals simplify synchronizationNoise floor (no input, VFS = 1VPP-DIFF):Dual-channel mode: -143.5, -148, -149.8dBFS/HzSingle-channel mode: -146.2, -150.3, -152.2dBFS/HzBuffered analog inputs with VCMI of 0V:Analog input bandwidth (–3dB): 8GHzFull-scale input voltage (VFS, default): 0.8VPPNoiseless aperture delay (TAD) adjustment:Precise sampling control: 19fs stepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTimestamp for sample markingPower consumption: 2.6, 2.8, 3W

Description

The ADC12DL500, ADC12DL1500 and ADC12DL2500 are a family of analog-to-digital converters (ADC) that can sample up to 500MSPS, 1.5GSPS, and 2.5GSPS in dual-channel mode and up to 1GSPS, 3GSPS, and 5GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and sample rate (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. The devices uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing. The ADC12DL500, ADC12DL1500 and ADC12DL2500 are a family of analog-to-digital converters (ADC) that can sample up to 500MSPS, 1.5GSPS, and 2.5GSPS in dual-channel mode and up to 1GSPS, 3GSPS, and 5GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and sample rate (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. The devices uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.