DS90CR288A Series
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Receiver - 85 MHz
Manufacturer: Texas Instruments
Catalog
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Receiver - 85 MHz
Key Features
• 20 to 85 MHz Shift Clock Support50% Duty Cycle on Receiver Output Clock2.5 / 0 ns Set & Hold Times on TxINPUTsLow Power Consumption±1V Common-Mode Range (around +1.2V)Narrow Bus Reduces Cable Size and CostUp to 2.38 Gbps ThroughputUp to 297.5 Mbytes/sec Bandwidth345 mV (typ) Swing LVDS Devices for Low EMIPLL Requires no External ComponentsRising Edge Data StrobeCompatible with TIA/EIA-644 LVDS StandardLow Profile 56-Lead TSSOP Package20 to 85 MHz Shift Clock Support50% Duty Cycle on Receiver Output Clock2.5 / 0 ns Set & Hold Times on TxINPUTsLow Power Consumption±1V Common-Mode Range (around +1.2V)Narrow Bus Reduces Cable Size and CostUp to 2.38 Gbps ThroughputUp to 297.5 Mbytes/sec Bandwidth345 mV (typ) Swing LVDS Devices for Low EMIPLL Requires no External ComponentsRising Edge Data StrobeCompatible with TIA/EIA-644 LVDS StandardLow Profile 56-Lead TSSOP Package
Description
AI
The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.
The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.
The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
