Catalog
Quad Channel 14-bit 500 Msps Telecom Receiver IC
Key Features
• Quad Channel14-Bit ResolutionMaximum Clock Rate: 500 MSPSInput Bandwidth (3 dB): 900 MHzOn-Chip DitherAnalog Input Buffer with High-Impedance InputOutput Options:Rx: Decimate-by-2 and -4 Options with Low-Pass Filter200-MHz Complex Bandwidth or 100-MHzReal Bandwidth SupportDPD FB: Burst Mode with 14-Bit Output1.9-VPPDifferential Full-Scale InputJESD204B Interface:Subclass 1 Support1 Lane per ADC Up to 10 GbpsDedicated SYNC pin for pair of channelsSupport for Multi-Chip Synchronization72-Pin VQFN Package (10 mm × 10 mm)Key Specifications:Power Dissipation: 675 mW/chSpectral Performance (Un-decimated)fIN= 190 MHz IF at –1 dBFS:SNR: 70.4 dBFSNSD: –154.4 dBFS/HzSFDR: 86 dBc (HD2, HD3),95 dBFS (non HD2, HD3)fIN= 370 MHz IF at –3 dBFS:SNR: 68.5 dBFSNSD: –152.5 dBFS/HzSFDR: 81 dBc (HD2, HD3),86 dBFS (non HD2, HD3)Quad Channel14-Bit ResolutionMaximum Clock Rate: 500 MSPSInput Bandwidth (3 dB): 900 MHzOn-Chip DitherAnalog Input Buffer with High-Impedance InputOutput Options:Rx: Decimate-by-2 and -4 Options with Low-Pass Filter200-MHz Complex Bandwidth or 100-MHzReal Bandwidth SupportDPD FB: Burst Mode with 14-Bit Output1.9-VPPDifferential Full-Scale InputJESD204B Interface:Subclass 1 Support1 Lane per ADC Up to 10 GbpsDedicated SYNC pin for pair of channelsSupport for Multi-Chip Synchronization72-Pin VQFN Package (10 mm × 10 mm)Key Specifications:Power Dissipation: 675 mW/chSpectral Performance (Un-decimated)fIN= 190 MHz IF at –1 dBFS:SNR: 70.4 dBFSNSD: –154.4 dBFS/HzSFDR: 86 dBc (HD2, HD3),95 dBFS (non HD2, HD3)fIN= 370 MHz IF at –3 dBFS:SNR: 68.5 dBFSNSD: –152.5 dBFS/HzSFDR: 81 dBc (HD2, HD3),86 dBFS (non HD2, HD3)
Description
AI
The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD observation receiver.
The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.
The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD observation receiver.
The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.
