OMAP3503 Series

Sitara processor: Arm Cortex-A8, LPDDR

Catalog

Sitara processor: Arm Cortex-A8, LPDDR

Part	Package / Case	Speed	Co-Processors/DSP	Number of Cores/Bus Width	Supplier Device Package	Core Processor	RAM Controllers	Display & Interface Controllers	Mounting Type	Operating Temperature [Min]	Operating Temperature [Max]	USB	Voltage - I/O	Additional Interfaces	Operating Temperature [custom]
Texas Instruments OMAP3503ECUS	423-LFBGA FCBGA	600 MHz	Multimedia NEON™ SIMD	1 Core 32 Bit	423-FCBGA (16x16)	ARM® Cortex®-A8	LPDDR	LCD	Surface Mount	0 °C	90 °C	USB 1.x (3) USB 2.0 (1)	1.8 V 3 V	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART
Texas Instruments OMAP3503ECBBA	515-VFBGA FCBGA	600 MHz	Multimedia NEON™ SIMD	1 Core 32 Bit	515-POP-FCBGA (12x12)	ARM® Cortex®-A8	LPDDR	LCD	Surface Mount			USB 1.x (3) USB 2.0 (1)	1.8 V 3 V	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	-40 °C 105 °C
Texas Instruments OMAP3503ECBB	515-VFBGA FCBGA	600 MHz	Multimedia NEON™ SIMD	1 Core 32 Bit	515-POP-FCBGA (12x12)	ARM® Cortex®-A8	LPDDR	LCD	Surface Mount	0 °C	90 °C	USB 1.x (3) USB 2.0 (1)	1.8 V 3 V	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART

Catalog

Sitara processor: Arm Cortex-A8, LPDDR

Key Features

• OMAP3 Devices:OMAP™ 3 ArchitectureMPU SubsystemUp to 720-MHz ARM® Cortex™-A8 CoreNEON™ SIMD CoprocessorPowerVR® SGX™ Graphics AcceleratorTile-Based Architecture Delivering up to 1 MPoly/secUniversal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader FunctionalityIndustry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0Fine-Grained Task Switching, Load Balancing, and Power ManagementProgrammable High-Quality Image Anti-AliasingFully Software-Compatible with ARM9™Commercial and Extended Temperature GradesARM Cortex-A8 CoreARMv7 ArchitectureTrustZone®Thumb®-2MMU EnhancementsIn-Order, Dual-Issue, Superscalar Microprocessor CoreNEON Multimedia ArchitectureOver 2x Performance of ARMv6 SIMDSupports Both Integer and Floating-Point SIMDJazelle® RCT Execution Environment ArchitectureDynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return StackEmbedded Trace Macrocell (ETM) Support for Noninvasive DebugARM Cortex-A8 Memory Architecture:-KB Instruction Cache (4-Way Set-Associative)-KB Data Cache (4-Way Set-Associative)-KB L2 Cache112KB of ROM64KB of Shared SRAMEndianess:ARM Instructions – Little EndianARM Data – ConfigurableExternal Memory Interfaces:General Purpose Memory Controller (GPMC)16-Bit-Wide Multiplexed Address and Data BusUp to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select PinGlueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAMFlexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)Camera Image Signal Processor (ISP)CCD and CMOS Imager InterfaceMemory Data InputBT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 InterfaceGlueless Interface to Common Video DecodersResize EngineResize Images From 1/4x to 4xSeparate Horizontal and Vertical ControlDisplay SubsystemParallel Digital OutputUp to 24-Bit RGBHD Maximum ResolutionSupports Up to 2 LCD PanelsSupport for Remote Frame Buffer Interface (RFBI) LCD Panels2 10-Bit Digital-to-Analog Converters (DACs) Supporting:Composite NTSC and PAL VideoLuma and Chroma Separate Video (S-Video)Rotation 90-, 180-, and 270-DegreesResize Images From 1/4x to 8xColor Space Converter8-Bit Alpha BlendingSerial Communication5 Multichannel Buffered Serial Ports (McBSPs)512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)5-KB Transmit and Receive Buffer (McBSP2)SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix OperationsDirect Interface to I2S and PCM Device and TDM Buses128-Channel Transmit and Receive ModeFour Master or Slave Multichannel Serial Port Interface (McSPI) PortsHigh-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)High-, Full-, and Low-Speed Multiport USB Host Subsystem12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial InterfaceOne HDQ™/1-Wire® InterfaceUARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) ControllersRemovable Media Interfaces:Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)Comprehensive Power, Reset, and Clock ManagementSmartReflex™ TechnologyDynamic Voltage and Frequency Scaling (DVFS)Test InterfacesIEEE 1149.1 (JTAG) Boundary-Scan CompatibleETM InterfaceSerial Data Transport Interface (SDTI)12 32-Bit General-Purpose Timers2 32-Bit Watchdog Timers1 32-Bit 32-kHz Sync TimerUp to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)5-nm CMOS TechnologiesPackage-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)Discrete Memory InterfacePackages:1.8-V I/O and 3.0-V (MMC1 Only),Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.OMAP3 Devices:OMAP™ 3 ArchitectureMPU SubsystemUp to 720-MHz ARM® Cortex™-A8 CoreNEON™ SIMD CoprocessorPowerVR® SGX™ Graphics AcceleratorTile-Based Architecture Delivering up to 1 MPoly/secUniversal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader FunctionalityIndustry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0Fine-Grained Task Switching, Load Balancing, and Power ManagementProgrammable High-Quality Image Anti-AliasingFully Software-Compatible with ARM9™Commercial and Extended Temperature GradesARM Cortex-A8 CoreARMv7 ArchitectureTrustZone®Thumb®-2MMU EnhancementsIn-Order, Dual-Issue, Superscalar Microprocessor CoreNEON Multimedia ArchitectureOver 2x Performance of ARMv6 SIMDSupports Both Integer and Floating-Point SIMDJazelle® RCT Execution Environment ArchitectureDynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return StackEmbedded Trace Macrocell (ETM) Support for Noninvasive DebugARM Cortex-A8 Memory Architecture:-KB Instruction Cache (4-Way Set-Associative)-KB Data Cache (4-Way Set-Associative)-KB L2 Cache112KB of ROM64KB of Shared SRAMEndianess:ARM Instructions – Little EndianARM Data – ConfigurableExternal Memory Interfaces:General Purpose Memory Controller (GPMC)16-Bit-Wide Multiplexed Address and Data BusUp to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select PinGlueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAMFlexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)Camera Image Signal Processor (ISP)CCD and CMOS Imager InterfaceMemory Data InputBT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 InterfaceGlueless Interface to Common Video DecodersResize EngineResize Images From 1/4x to 4xSeparate Horizontal and Vertical ControlDisplay SubsystemParallel Digital OutputUp to 24-Bit RGBHD Maximum ResolutionSupports Up to 2 LCD PanelsSupport for Remote Frame Buffer Interface (RFBI) LCD Panels2 10-Bit Digital-to-Analog Converters (DACs) Supporting:Composite NTSC and PAL VideoLuma and Chroma Separate Video (S-Video)Rotation 90-, 180-, and 270-DegreesResize Images From 1/4x to 8xColor Space Converter8-Bit Alpha BlendingSerial Communication5 Multichannel Buffered Serial Ports (McBSPs)512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)5-KB Transmit and Receive Buffer (McBSP2)SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix OperationsDirect Interface to I2S and PCM Device and TDM Buses128-Channel Transmit and Receive ModeFour Master or Slave Multichannel Serial Port Interface (McSPI) PortsHigh-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)High-, Full-, and Low-Speed Multiport USB Host Subsystem12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial InterfaceOne HDQ™/1-Wire® InterfaceUARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) ControllersRemovable Media Interfaces:Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)Comprehensive Power, Reset, and Clock ManagementSmartReflex™ TechnologyDynamic Voltage and Frequency Scaling (DVFS)Test InterfacesIEEE 1149.1 (JTAG) Boundary-Scan CompatibleETM InterfaceSerial Data Transport Interface (SDTI)12 32-Bit General-Purpose Timers2 32-Bit Watchdog Timers1 32-Bit 32-kHz Sync TimerUp to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)5-nm CMOS TechnologiesPackage-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)Discrete Memory InterfacePackages:1.8-V I/O and 3.0-V (MMC1 Only),Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

Description

devices are based on the enhanced OMAP 3 architecture. The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: The device supports high-level operating systems (HLOSs), such as: This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device: The device also offers: OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences). This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections: devices are based on the enhanced OMAP 3 architecture. The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: The device supports high-level operating systems (HLOSs), such as: This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device: The device also offers: OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences). This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections: