CDCVF310 Series
High performance 1:10 clock buffer for general purpose applications with support up to 85C
Manufacturer: Texas Instruments
Catalog
High performance 1:10 clock buffer for general purpose applications with support up to 85C
Key Features
• High-Performance 1:10 Clock DriverPin-to-Pin Skew < 100 ps at VDD3.3 VVDDRange = 2.3 V to 3.6 VInput Clock Up To 200 MHz (See Figure 7)Operating Temperature Range -40°C to 85°COutput Enable Glitch SuppressionDistributes One Clock Input to Two Banks of Five OutputsPackaged in 24-Pin TSSOPPin-to-Pin Compatible to the CDCVF2310,Except the R = 22-Series DampingResistors at YnAPPLICATIONSGeneral-Purpose ApplicationsHigh-Performance 1:10 Clock DriverPin-to-Pin Skew < 100 ps at VDD3.3 VVDDRange = 2.3 V to 3.6 VInput Clock Up To 200 MHz (See Figure 7)Operating Temperature Range -40°C to 85°COutput Enable Glitch SuppressionDistributes One Clock Input to Two Banks of Five OutputsPackaged in 24-Pin TSSOPPin-to-Pin Compatible to the CDCVF2310,Except the R = 22-Series DampingResistors at YnAPPLICATIONSGeneral-Purpose Applications
Description
AI
The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.
The CDCVF310 is characterized for operation from -40°C to 85°C.
The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.
The CDCVF310 is characterized for operation from -40°C to 85°C.