ADS6124 Series

12-Bit, 105-MSPS Analog-to-Digital Converter (ADC)

Catalog

12-Bit, 105-MSPS Analog-to-Digital Converter (ADC)

Part	Architecture	Supplier Device Package	Number of A/D Converters	Reference Type	Mounting Type	Configuration	Sampling Rate (Per Second)	Ratio - S/H:ADC	Data Interface	Operating Temperature [Max]	Operating Temperature [Min]	Number of Inputs	Package / Case	Number of Bits	Input Type	Voltage - Supply, Digital [Min]	Voltage - Supply, Digital [Max]	Voltage - Supply, Analog [Max]	Voltage - Supply, Analog [Min]	Power (Typ) @ Conditions	Supplied Contents	Input Range	Utilized IC / Part
Texas Instruments ADS6124IRHBR	Pipelined	32-VQFN (5x5)	1	Internal	Surface Mount	S/H-ADC	105 M	1:1	LVDS - Parallel Parallel	85 °C	-40 °C	1	32-VFQFN Exposed Pad	12 bits	Differential	1.65 V	3.6 V	3.6 V	3 V
Texas Instruments ADS6124IRHB25	Pipelined	32-VQFN (5x5)	1	Internal	Surface Mount	S/H-ADC	105 M	1:1	LVDS - Parallel Parallel	85 °C	-40 °C	1	32-VFQFN Exposed Pad	12 bits	Differential	1.65 V	3.6 V	3.6 V	3 V
Texas Instruments ADS6124IRHBT	Pipelined	32-VQFN (5x5)	1	Internal	Surface Mount	S/H-ADC	105 M	1:1	LVDS - Parallel Parallel	85 °C	-40 °C	1	32-VFQFN Exposed Pad	12 bits	Differential	1.65 V	3.6 V	3.6 V	3 V
Texas Instruments ADS6124EVM			1				105 M		Parallel Serial					12 bits						374 mW	Board(s)	2 Vpp	ADS6124

Catalog

12-Bit, 105-MSPS Analog-to-Digital Converter (ADC)

Key Features

• Maximum Sample Rate: 125 MSPS12-Bit Resolution with No Missing Codes3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-OffParallel CMOS and Double Data Rate (DDR) LVDS Output OptionsSupports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPPClock Duty Cycle StabilizerInternal Reference with Support for External ReferenceNo External Decoupling Required for ReferencesProgrammable Output Clock Position and Drive Strength to Ease Data Capture3.3 V Analog and 1.8 V to 3.3 V Digital Supply32-QFN Package (5 mm × 5 mm)Pin Compatible 12-Bit Family (ADS612X)APPLICATIONSWireless Communications InfrastructureSoftware Defined RadioPower Amplifier Linearization802.16d/eTest and Measurement InstrumentationHigh Definition VideoMedical ImagingRadar SystemsMaximum Sample Rate: 125 MSPS12-Bit Resolution with No Missing Codes3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-OffParallel CMOS and Double Data Rate (DDR) LVDS Output OptionsSupports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPPClock Duty Cycle StabilizerInternal Reference with Support for External ReferenceNo External Decoupling Required for ReferencesProgrammable Output Clock Position and Drive Strength to Ease Data Capture3.3 V Analog and 1.8 V to 3.3 V Digital Supply32-QFN Package (5 mm × 5 mm)Pin Compatible 12-Bit Family (ADS612X)APPLICATIONSWireless Communications InfrastructureSoftware Defined RadioPower Amplifier Linearization802.16d/eTest and Measurement InstrumentationHigh Definition VideoMedical ImagingRadar Systems

Description

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies. It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges. The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability. The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up. ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported. The devices are specified over the industrial temperature range (-40°C to 85°C). ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies. It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges. The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability. The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up. ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported. The devices are specified over the industrial temperature range (-40°C to 85°C).