FDC6304P Series

Dual P-Channel Digital FET -25V, -0.46A, 1.1Ω

Catalog

Dual P-Channel Digital FET -25V, -0.46A, 1.1Ω

Part	Rds On (Max) @ Id, Vgs [Max]	Gate Charge (Qg) (Max) @ Vgs [Max]	Drain to Source Voltage (Vdss)	Mounting Type	Package / Case	Input Capacitance (Ciss) (Max) @ Vds	FET Feature	Operating Temperature [Min]	Operating Temperature [Max]	Power - Max [Max]	Vgs(th) (Max) @ Id	Technology	Supplier Device Package	Configuration	Current - Continuous Drain (Id) @ 25°C
ON Semiconductor FDC6304P	1.1 Ohm	1.5 nC	25 V	Surface Mount	SOT-23-6 Thin TSOT-23-6	62 pF	Logic Level Gate	-55 °C	150 °C	700 mW	1.5 V	MOSFET (Metal Oxide)	SuperSOT™-6	2 P-Channel	460 mA
ON Semiconductor FDC6304P	1.1 Ohm	1.5 nC	25 V	Surface Mount	SOT-23-6 Thin TSOT-23-6	62 pF	Logic Level Gate	-55 °C	150 °C	700 mW	1.5 V	MOSFET (Metal Oxide)	SuperSOT™-6	2 P-Channel	460 mA

Catalog

Dual P-Channel Digital FET -25V, -0.46A, 1.1Ω

Key Features

-25 V, -0.46 A continuous, -1.0 A Peak

• RDS(ON)= 1.5 Ω @ VGS= -2.7 V

• RDS(ON)= 1.1 Ω @ VGS= -4.5 V

• Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th)< 1.5 V

• Gate-Source Zener for ESD ruggedness. >6kV Human Body Model

Description

These P-Channel enhancement mode field effect transistor are produced using a proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance at low gate drive conditions. This device is designed especially for application in battery power applications such as notebook computers and cellular phones. This device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts.