Catalog
14-Bit, 160-MSPS Analog-to-Digital Converter (ADC)
Key Features
• Output Interface:Single-Lane and Dual-Lane InterfacesMaximum Data Rate: 3.125 GbpsMeets JEDEC JESD204A SpecificationCML Outputs with Current Programmable from 2 mA to 32 mAPower Dissipation:583 mW at 160 MSPS in Dual-Lane ModePower Scales Down with Clock RateInput Interface: Buffered Analog InputsSNR at 185-MHz IF: –72.7 dBFSAnalog Input Dynamic Range: 2 VPPReference Support:External and Internal (Trimmed)Supply:Analog and Digital: 1.8 VInput Buffer: 3.3 VProgrammable Digital Gain: 0 dB to 6 dBOutput: Straight Offset Binary orTwos ComplementPackage: 6-mm × 6-mm QFN-40Output Interface:Single-Lane and Dual-Lane InterfacesMaximum Data Rate: 3.125 GbpsMeets JEDEC JESD204A SpecificationCML Outputs with Current Programmable from 2 mA to 32 mAPower Dissipation:583 mW at 160 MSPS in Dual-Lane ModePower Scales Down with Clock RateInput Interface: Buffered Analog InputsSNR at 185-MHz IF: –72.7 dBFSAnalog Input Dynamic Range: 2 VPPReference Support:External and Internal (Trimmed)Supply:Analog and Digital: 1.8 VInput Buffer: 3.3 VProgrammable Digital Gain: 0 dB to 6 dBOutput: Straight Offset Binary orTwos ComplementPackage: 6-mm × 6-mm QFN-40
Description
AI
The ADS61JB46 is a high-performance, low-power, single-channel, analog-to-digital converter with an integrated JESD204A output interface. Available in a 6-mm × 6-mm QFN package, with both single-lane and dual-lane output modes, the device offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per the IEEE standard 802.3-2002 part 3, clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample-and-hold switches and higher and more consistent input impedance.
The device is specified over the industrial temperature range (–40°C to +85°C).
The ADS61JB46 is a high-performance, low-power, single-channel, analog-to-digital converter with an integrated JESD204A output interface. Available in a 6-mm × 6-mm QFN package, with both single-lane and dual-lane output modes, the device offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per the IEEE standard 802.3-2002 part 3, clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample-and-hold switches and higher and more consistent input impedance.
The device is specified over the industrial temperature range (–40°C to +85°C).
