AD9629 Series
12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
Manufacturer: Analog Devices
Catalog
12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
Key Features
• 1.8 V analog supply operation
• 1.8 V to 3.3 V output supply
• SNR71.3 dBFS at 9.7 MHz input69.0 dBFS at 200 MHz input
• 71.3 dBFS at 9.7 MHz input
• 69.0 dBFS at 200 MHz input
• SFDR95 dBc at 9.7 MHz input83 dBc at 200 MHz input
• 95 dBc at 9.7 MHz input
• 83 dBc at 200 MHz input
• Low power45 mW at 20 MSPS85 mW at 80 MSPS
• 45 mW at 20 MSPS
• 85 mW at 80 MSPS
• Differential input with 700 MHz bandwidth
• On-chip voltage reference and sample-and-hold circuit
• 2 V p-p differential analog input
• DNL = ±0.16 LSB
• Serial port control optionsOffset binary, gray code, or twos complement data formatInteger 1, 2, or 4 input clock dividerBuilt-in selectable digital test pattern generationEnergy-saving power-down modesData clock out with programmable clock and data alignment
• Offset binary, gray code, or twos complement data format
• Integer 1, 2, or 4 input clock divider
• Built-in selectable digital test pattern generation
• Energy-saving power-down modes
• Data clock out with programmable clock and data alignment
Description
AI
The AD9629 is a monolithic, single channel 1.8 V supply, 12-bit, 20 MSPS/40 MSPS/65MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported.The AD9629 is available in a 32-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).ApplicationsCommunicationsDiversity radio systemsMultimode digital receiversGSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMASmart antenna systemsBattery-powered instrumentsHand held scope metersPortable medical imagingUltrasoundRadar/LIDARPET/SPECT imagingProduct Highlights1. The AD9629 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.3. A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D11 to D0) timing and offset adjustments, and voltage reference modes.4. The AD9629 is packaged in a 32-lead RoHS compliant LFCSP that is pin compatible with the AD9609 10-bit ADC and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.
