ADS4229 Series

Dual-Channel, 12-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

Catalog

Dual-Channel, 12-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

Part	Number of Inputs	Sampling Rate (Per Second)	Voltage - Supply, Analog [Max]	Voltage - Supply, Analog [Min]	Architecture	Voltage - Supply, Digital [Min]	Voltage - Supply, Digital [Max]	Data Interface	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Input Type	Configuration	Features	Number of Bits	Supplier Device Package	Ratio - S/H:ADC	Number of A/D Converters	Package / Case	Reference Type	Supplied Contents	Input Range	Utilized IC / Part
Texas Instruments ADS4229IRGCR	2	250 M	1.9 V	1.7 V	Pipelined	1.7 V	1.9 V	LVDS - Parallel Parallel	85 °C	-40 °C	Surface Mount	Differential	S/H-ADC	Simultaneous Sampling	12 bits	64-VQFN (9x9)	1:1	2	64-VFQFN Exposed Pad	Internal
Texas Instruments ADS4229IRGCT	2	250 M	1.9 V	1.7 V	Pipelined	1.7 V	1.9 V	LVDS - Parallel Parallel	85 °C	-40 °C	Surface Mount	Differential	S/H-ADC	Simultaneous Sampling	12 bits	64-VQFN (9x9)	1:1	2	64-VFQFN Exposed Pad	Internal
Texas Instruments ADS4229EVM		250 M						USB							12 bits			2			Board(s)	2 Vpp	ADS4229
Texas Instruments ADS4229IRGC25	2	250 M	1.9 V	1.7 V	Pipelined	1.7 V	1.9 V	LVDS - Parallel Parallel	85 °C	-40 °C	Surface Mount	Differential	S/H-ADC	Simultaneous Sampling	12 bits	64-VQFN (9x9)	1:1	2	64-VFQFN Exposed Pad	Internal

Catalog

Dual-Channel, 12-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

Key Features

• Maximum Sample Rate: 250 MSPSUltralow Power with Single 1.8-V Supply:545-mW Total Power at 250 MSPSHigh Dynamic Performance:80.8-dBc SFDR at 170 MHz69.4-dBFS SNR at 170 MHzCrosstalk: > 90 dB at 185 MHzProgrammable Gain Up to 6 dB forSNR and SFDR Trade-offDC Offset CorrectionOutput Interface Options:1.8-V Parallel CMOS InterfaceDDR LVDS With Programmable Swing:Standard Swing: 350 mVLow Swing: 200 mVSupports Low Input Clock AmplitudeDown to 200 mVPPPackage: 9-mm × 9-mm, 64-Pin Quad FlatNo-Lead (QFN) PackageMaximum Sample Rate: 250 MSPSUltralow Power with Single 1.8-V Supply:545-mW Total Power at 250 MSPSHigh Dynamic Performance:80.8-dBc SFDR at 170 MHz69.4-dBFS SNR at 170 MHzCrosstalk: > 90 dB at 185 MHzProgrammable Gain Up to 6 dB forSNR and SFDR Trade-offDC Offset CorrectionOutput Interface Options:1.8-V Parallel CMOS InterfaceDDR LVDS With Programmable Swing:Standard Swing: 350 mVLow Swing: 200 mVSupports Low Input Clock AmplitudeDown to 200 mVPPPackage: 9-mm × 9-mm, 64-Pin Quad FlatNo-Lead (QFN) Package

Description

The ADS4229 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4229 well-suited for multi-carrier, wide-bandwidth communications applications. The ADS4229 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available in a compact QFN-64 PowerPAD™ package. The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4229 is specified over the industrial temperature range (–40°C to +85°C). The ADS4229 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4229 well-suited for multi-carrier, wide-bandwidth communications applications. The ADS4229 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available in a compact QFN-64 PowerPAD™ package. The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4229 is specified over the industrial temperature range (–40°C to +85°C).