ADC12QJ1600-EP Series
Enhanced-product, quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface
Manufacturer: Texas Instruments
Catalog
Enhanced-product, quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface
Key Features
• High reliability enhanced product:Controlled BaselineOne Assembly and Test SiteOne Fabrication Site–55°C to 125°C Temperature RangeExtended Product Life CycleExtended Product-Change NotificationProduct TraceabilityADC Core:Resolution: 12 BitMaximum sampling rate: 1.6 GSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1 dBFS):SNR (100 MHz): 57.4 dBFSENOB (100 MHz): 9.1 BitsSFDR (100 MHz): 64 dBcNoise floor (–20 dBFS): –147 dBFSFull-scale input voltage: 800 mVPP-DIFFFull-power input bandwidth: 6 GHzJESD204C Serial data interface:Support for 2 to 8 total SerDes lanesMaximum baud-rate: 17.16 Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2 GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (1 GSPS): 1.9WPower supplies: 1.1 V, 1.9 VHigh reliability enhanced product:Controlled BaselineOne Assembly and Test SiteOne Fabrication Site–55°C to 125°C Temperature RangeExtended Product Life CycleExtended Product-Change NotificationProduct TraceabilityADC Core:Resolution: 12 BitMaximum sampling rate: 1.6 GSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1 dBFS):SNR (100 MHz): 57.4 dBFSENOB (100 MHz): 9.1 BitsSFDR (100 MHz): 64 dBcNoise floor (–20 dBFS): –147 dBFSFull-scale input voltage: 800 mVPP-DIFFFull-power input bandwidth: 6 GHzJESD204C Serial data interface:Support for 2 to 8 total SerDes lanesMaximum baud-rate: 17.16 Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2 GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (1 GSPS): 1.9WPower supplies: 1.1 V, 1.9 V
Description
AI
ADC12QJ1600-EP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of multi-channel communications systems.
Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
ADC12QJ1600-EP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of multi-channel communications systems.
Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
