STM32MP257F Series

STM32MP25xC/F devices are based on the high-performance single or dual-core Arm® Cortex®-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex®‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex®‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency. STM32MP25xC/F devices also embed a Cortex®-M33 32-bit RISC core operating at up to 400 MHz frequency. The Cortex®-M33 core features a floating point unit (FPU) single precision which supports Arm® single-precision data-processing instructions, and data types. The Cortex®-M33 supports a full set of DSP instructions, TrustZone®, and a memory protection unit (MPU) which enhances application security. The devices also embed a Cortex®-M0+ 32-bit RISC core operating at up to 200 MHz frequency (16 MHz when running from backup regulator). This processor is located in the SmartRun domain, and can be used to ensure very-low-power peripheral activity when all other processors and domains are stopped. STM32MP25xC/F devices can also embed a 3D graphic processing unit (VeriSilicon®, OpenGL ES 3.1, Vulkan 1.3, OpenCL 3.0, OpenVX 1.3) running at up to 900 MHz, with performances up to 150 Mtriangle/s, 900 Mpixel/s. The graphic processing unit can provide a neural processor unit (VeriSilicon®, TensorFlowLite, ONNX, Linux NN) running at up to 900 MHz. STM32MP25xC/F devices provide an external SDRAM interface supporting external memories up to 32‑Gbit density (4 Gbytes), 16- or 32-bit DDR3L up to 1066 MHz, 16- or 32-bit LPDDR4 or DDR4 up to 1200 MHz. The SDRAM content can be encrypted with AES-128. The devices incorporate high-speed embedded memories: 808 Kbytes of internal SRAM (including 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video SRAM (which can be used as general purpose), two banks of 128 Kbytes each of AHB SRAM, three banks of 8, 8, and 16 Kbytes of AHB SRAM in SmartRun domain, 128 Kbytes of AHB SRAM in backup domain, and 8 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix, and a 128/64-bit multi-layer AXI interconnect supporting access to internal and external memories. Each device offers three ADCs, a low-power secure RTC, 12 general-purpose 16-bit timers, 4 general-purpose 32‑bit timers, three PWM timers for motor control, five low-power timers, and a true random number generator (RNG) , and cryptographic acceleration cells. STM32MP25xC/F devices offer a video encoder and a video decoder. The devices support 8 multi-function digital filters (MDF), and one dedicated audio-digital filter with sound-activity detection (ADF). The devices feature the following standard and advanced communication interfaces. Standard peripherals Advanced peripherals including A comprehensive set of power-saving mode allows the design of low-power applications. STM32MP25xC/F devices are proposed in various packages up to 436 balls with 0.5 mm to 0.8 mm pitch. The set of included peripherals can change with the selected device. These features make STM32MP25xC/F devices suitable for a wide range of consumer, industrial, white goods and medical applications.