CD74HCT109 Series

High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset

Catalog

High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset

Part	Input Capacitance	Trigger Type	Number of Elements	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Current - Quiescent (Iq)	Type	Function	Package / Case	Package / Case	Package / Case	Number of Bits per Element	Max Propagation Delay @ V, Max CL	Output Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Clock Frequency	Supplier Device Package	Package / Case [x]	Package / Case [y]
Texas Instruments CD74HCT109E	10 pF	Positive Edge	2	4.5 V	5.5 V	125 °C	-55 °C	4 çA	JK Type	Reset Set(Preset)	0.3 in	16-DIP	7.62 mm	1	40 ns	Complementary	4 mA	4 mA	Through Hole	54 MHz	16-PDIP
Texas Instruments CD74HCT109MT	10 pF	Positive Edge	2	4.5 V	5.5 V	125 °C	-55 °C	4 çA	JK Type	Reset Set(Preset)		16-SOIC		1	40 ns	Complementary	4 mA	4 mA	Surface Mount	54 MHz	16-SOIC	0.154 in	3.9 mm

Catalog

High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset

Key Features

• Asynchronous Set and ResetSchmitt Trigger Clock InputsTypical fMAX= 54MHz at VCC= 5V, CL= 15pF, A = 25°CFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHAsynchronous Set and ResetSchmitt Trigger Clock InputsTypical fMAX= 54MHz at VCC= 5V, CL= 15pF, A = 25°CFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOH

Description

The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.