AD9644 Series

14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter

Catalog

14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter

Part	Mounting Type	Voltage - Supply, Digital [Min]	Voltage - Supply, Digital [Max]	Architecture	Features	Sampling Rate (Per Second)	Configuration	Data Interface	Supplier Device Package	Reference Type	Ratio - S/H:ADC	Operating Temperature [Max]	Operating Temperature [Min]	Number of Inputs	Voltage - Supply, Analog [Max]	Voltage - Supply, Analog [Min]	Input Type	Package / Case	Number of Bits	Number of A/D Converters
Analog Devices AD9644BCPZRL7-80	Surface Mount	1.7 V	1.9 V	Pipelined	Simultaneous Sampling	80 M	S/H-ADC	JESD204A	48-LFCSP-VQ (7x7)	Internal	1:1	85 °C	-40 °C	2	1.9 V	1.7 V	Differential	48-VFQFN Exposed Pad CSP	14	2
Analog Devices AD9644CCPZ-80	Surface Mount	1.7 V	1.9 V	Pipelined	Simultaneous Sampling	80 M	S/H-ADC	JESD204A	48-LFCSP-VQ (7x7)	Internal	1:1	85 °C	-40 °C	2	1.9 V	1.7 V	Differential	48-VFQFN Exposed Pad CSP	14	2
Analog Devices AD9644CCPZRL7-80	Surface Mount	1.7 V	1.9 V	Pipelined	Simultaneous Sampling	80 M	S/H-ADC	JESD204A	48-LFCSP-VQ (7x7)	Internal	1:1	85 °C	-40 °C	2	1.9 V	1.7 V	Differential	48-VFQFN Exposed Pad CSP	14	2
Analog Devices AD9644BCPZRL7-155	Surface Mount	1.7 V	1.9 V	Pipelined	Simultaneous Sampling	155 M	S/H-ADC	JESD204A	48-LFCSP-VQ (7x7)	Internal	1:1	85 °C	-40 °C	2	1.9 V	1.7 V	Differential	48-VFQFN Exposed Pad CSP	14	2
Analog Devices AD9644BCPZ-155	Surface Mount	1.7 V	1.9 V	Pipelined	Simultaneous Sampling	155 M	S/H-ADC	JESD204A	48-LFCSP-VQ (7x7)	Internal	1:1	85 °C	-40 °C	2	1.9 V	1.7 V	Differential	48-VFQFN Exposed Pad CSP	14	2

Catalog

14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter

Key Features

• JESD204A coded serial digital outputs

• SNR = 73.7 dBFS at 70 MHz and 80 MSPS

• SNR = 71.7 dBFS at 70 MHz and 155 MSPS

• SFDR = 92 dBc at 70 MHz and 80 MSPS

• SFDR = 92 dBc at 70 MHz and 155 MSPS

• Low power: 423 mW at 80 MSPS, 567 mW at 155 MSPS

• 1.8 V supply operation

• IF sampling frequencies to 250 MHz

• Integer 1-to-8 input clock divider−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS

• -150.3 dBFS/Hz input noise at 180 MHz and 155 MSPS

• Please see data sheet for additional features

Description

The AD9644 is a dual, 14-bit, analog-to-digital converter (ADC) with a high speed serial output interface and sampling speeds of either 80 MSPS or 155 MSPS.The AD9644 is designed to support communications appli-cations where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.By default, the ADC output data is routed directly to the two external JESD204A serial output ports. These outputs are at CML voltage levels. Two modes are supported such that output coded data is either sent through one data link or two. (L = 1; F = 4 or L = 2; F = 2). Independent synchronization inputs (DSYNC) are provided for each channel.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9644 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.This product is protected by a U.S. patent.ApplicationsCommunicationsDiversity radio systemsMultimode digital receivers (3G and 4G)GSM, EDGE, W-CDMA, LTE,CDMA2000, WiMAX, TD-SCDMAI/Q demodulation systemsSmart antenna systemsGeneral-purpose software radiosBroadband data applicationsUltrasound equipmentProduct HighlightsAn on-chip PLL allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding data rate clock.The configurable JESD204A output block supports up to 1.6 Gbps per channel data rate when using a dedicated data link per ADC or 3.2 Gbps data rate when using a single shared data link for both ADCs.Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz.Operation from a single 1.8 V power supply.Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.