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ADRF5545A

ADRF5545A Series

Dual-Channel, 2.4 GHz to 4.2 GHz Receiver Front End

Manufacturer: Analog Devices

Catalog

Dual-Channel, 2.4 GHz to 4.2 GHz Receiver Front End

Key Features

• Integrated dual-channel RF front end2-stage LNA and high power SPDT switchOn-chip bias and matchingSingle supply operation
• 2-stage LNA and high power SPDT switch
• On-chip bias and matching
• Single supply operation
• GainHigh gain mode: 32 dB typical at 3.6 GHzLow gain mode: 16 dB typical at 3.6 GHz
• High gain mode: 32 dB typical at 3.6 GHz
• Low gain mode: 16 dB typical at 3.6 GHz
• Low noise figureHigh gain mode: 1.45 dB typical at 3.6 GHzLow gain mode: 1.45 dB typical at 3.6 GHz
• High gain mode: 1.45 dB typical at 3.6 GHz
• Low gain mode: 1.45 dB typical at 3.6 GHz
• High isolationRXOUT-CHA and RXOUT-CHB: 47 dB typicalTERM-CHA and TERM-CHB: 52 dB typical
• RXOUT-CHA and RXOUT-CHB: 47 dB typical
• TERM-CHA and TERM-CHB: 52 dB typical
• Low insertion loss: 0.65 dB typical at 3.6 GHz
• High power handling at TCASE= 105°CFull lifetimeLTE average power (9 dB PAR): 40 dBmSingle event (<10 sec operation)LTE average power (9 dB PAR): 43 dBm
• Full lifetimeLTE average power (9 dB PAR): 40 dBm
• LTE average power (9 dB PAR): 40 dBm
• Single event (<10 sec operation)LTE average power (9 dB PAR): 43 dBm
• LTE average power (9 dB PAR): 43 dBm
• High OIP3: 32 dBm typical
• Power-down mode and low gain mode for LNA
• Low supply currentHigh gain mode: 86 mA typical at 5 VLow gain mode: 36 mA typical at 5 VPower-down mode: 12 mA typical at 5 V
• High gain mode: 86 mA typical at 5 V
• Low gain mode: 36 mA typical at 5 V
• Power-down mode: 12 mA typical at 5 V
• Positive logic control
• 6 mm × 6 mm, 40-lead LFCSP package

Description

AI
The ADRF5545A is a dual-channel, integrated radio frequency (RF), front-end multichip module designed for time division duplexing (TDD) applications that operates from 2.4 GHz to 4.2 GHz. The ADRF5545A is configured in dual channels with a cascading two-stage low noise amplifier (LNA) and a high power silicon single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure (NF) of 1.45 dB and a high gain of 32 dB at 3.6 GHz with an output third-order intercept point (OIP3) of 32 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 16 dB of gain at a lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.65 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (<10 sec) LNA protection operation.The device comes in an RoHS compliant, compact, 6 mm × 6 mm, 40-lead LFCSP package.ApplicationsWireless infrastructureTDD massive multiple input and multiple output and active antenna systemsTDD-based communication systems