TUSB1210-Q1 Series

Automotive USB2.0 high-speed 480-Mbps ULPI PHY transceiver

Catalog

Automotive USB2.0 high-speed 480-Mbps ULPI PHY transceiver

Part	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Data Rate	Receiver Hysteresis	Protocol	Package / Case	Duplex	Operating Temperature [Max]	Operating Temperature [Min]	Type	Mounting Type	Grade	Qualification	Utilized IC / Part	Function	Supplied Contents
Texas Instruments TUSB1210BRHBR	2.7 V	4.8 V	32-VQFN (5x5)	480 Mbps	50 mV	USB 2.0	32-VFQFN Exposed Pad	Half	85 °C	-40 °C	Transceiver	Surface Mount
Texas Instruments TUSB1210BRHBT	2.7 V	4.8 V	32-VQFN (5x5)	480 Mbps	50 mV	USB 2.0	32-VFQFN Exposed Pad	Half	85 °C	-40 °C	Transceiver	Surface Mount
Texas Instruments TUSB1210BRHBTQ1	2.7 V	4.8 V	32-VQFN (5x5)	480 Mbps	50 mV	USB 2.0	32-VFQFN Exposed Pad	Half	85 °C	-40 °C	Transceiver	Surface Mount	Automotive	AEC-Q100
Texas Instruments TUSB1210EVM											Interface				TUSB1210	Transceiver USB	Board(s)

Catalog

Automotive USB2.0 high-speed 480-Mbps ULPI PHY transceiver

Key Features

• AEC-Q100 Qualified with:Temperature Grade 3: –40°C to 85°CHBM ESD Classification 1CCDM ESD Classification C4BUSB2.0 PHY Transceiver Chip, Designed to Interfacewith a USB Controller via a ULPI 12-pin Interface,Fully Compliant With:Universal Serial Bus SpecificationRev. 2.0On-The-Go Supplement to the USB2.0 SpecificationRev. 1.3UTMI+ Low Pin Interface (ULPI) SpecificationRev. 1.1DP/DM Line External Component Compensation(Patent #US7965100 B1)Interfaces to Host, Peripheral and OTG Device Cores;Optimized for Portable Devices or System ASICs withBuilt-in USB OTG Device CoreComplete USB OTG Physical Front-End that SupportsHost Negotiation Protocol (HNP) and Session RequestProtocol (SRP)ULPI Interface:I/O Interface (1.8 V) Optimized for Non-Terminated50 Ω Line ImpedanceULPI CLOCK Pin (60 MHz) Supports Both Inputand Output Clock ConfigurationsFully Programmable ULPI-Compliant Register SetAvailable in a 32-Pin Quad Flat No Lead[QFN (RHB)] PackageAEC-Q100 Qualified with:Temperature Grade 3: –40°C to 85°CHBM ESD Classification 1CCDM ESD Classification C4BUSB2.0 PHY Transceiver Chip, Designed to Interfacewith a USB Controller via a ULPI 12-pin Interface,Fully Compliant With:Universal Serial Bus SpecificationRev. 2.0On-The-Go Supplement to the USB2.0 SpecificationRev. 1.3UTMI+ Low Pin Interface (ULPI) SpecificationRev. 1.1DP/DM Line External Component Compensation(Patent #US7965100 B1)Interfaces to Host, Peripheral and OTG Device Cores;Optimized for Portable Devices or System ASICs withBuilt-in USB OTG Device CoreComplete USB OTG Physical Front-End that SupportsHost Negotiation Protocol (HNP) and Session RequestProtocol (SRP)ULPI Interface:I/O Interface (1.8 V) Optimized for Non-Terminated50 Ω Line ImpedanceULPI CLOCK Pin (60 MHz) Supports Both Inputand Output Clock ConfigurationsFully Programmable ULPI-Compliant Register SetAvailable in a 32-Pin Quad Flat No Lead[QFN (RHB)] Package

Description

The TUSB1210-Q1 is a USB2.0 transceiver chip, designed to interface with a USB controller via a ULPI interface. It supports all USB2.0 data rates (High-Speed 480 Mbps, Full-Speed 12 Mbps and Low-Speed 1.5 Mbps), and is compliant to both Host and Peripheral modes. It additionally supports a UART mode and legacy ULPI serial modes. TUSB1210-Q1 also supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The DP/DM external component compensation in the transmitter compensates for variations in the series impendence in order to match with the data line impedance and the receiver input impedance, to limit data reflections, and thereby, improve eye diagrams. The TUSB1210-Q1 is a USB2.0 transceiver chip, designed to interface with a USB controller via a ULPI interface. It supports all USB2.0 data rates (High-Speed 480 Mbps, Full-Speed 12 Mbps and Low-Speed 1.5 Mbps), and is compliant to both Host and Peripheral modes. It additionally supports a UART mode and legacy ULPI serial modes. TUSB1210-Q1 also supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The DP/DM external component compensation in the transmitter compensates for variations in the series impendence in order to match with the data line impedance and the receiver input impedance, to limit data reflections, and thereby, improve eye diagrams.