Catalog
4-channel bus LVDS transceiver
Key Features
• Bus LVDS SignalingPropagation Delay: Driver 2.3 ns Max, Receiver 3.2 ns MaxLow power CMOS Design100% Transition Time 1 ns Driver Typical, 1.3 ns Receiver TypicalHigh Signaling Rate Capability (above 155 Mbps)0.1 V to 2.3 V Common Mode Range forVID= 200 mV70 mV Receiver SensitivitySupports Open and Terminated Failsafe on Port Pins3.3-V OperationGlitch Free Power up/down (Driver & Receiver Disabled)Light Bus Loading (5 pF Typical) per Bus LVDS LoadBalanced Output ImpedanceProduct Offered in 44 Pin WQFN PackageHigh Impedance Bus Pins on Power Off(VCC= 0 V)Bus LVDS SignalingPropagation Delay: Driver 2.3 ns Max, Receiver 3.2 ns MaxLow power CMOS Design100% Transition Time 1 ns Driver Typical, 1.3 ns Receiver TypicalHigh Signaling Rate Capability (above 155 Mbps)0.1 V to 2.3 V Common Mode Range forVID= 200 mV70 mV Receiver SensitivitySupports Open and Terminated Failsafe on Port Pins3.3-V OperationGlitch Free Power up/down (Driver & Receiver Disabled)Light Bus Loading (5 pF Typical) per Bus LVDS LoadBalanced Output ImpedanceProduct Offered in 44 Pin WQFN PackageHigh Impedance Bus Pins on Power Off(VCC= 0 V)
Description
AI
The DS92LV040A is one in a series of Bus LVDS transceivers designed specifically for high speed, low power backplane or cable interfaces. The device operates from a single 3.3-V power supply and includes four differential line drivers and four receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.
The driver translates 3-V LVTTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation while consuming minimal power and reducing EMI. In addition, the differential signaling provides common mode noise rejection greater than ±1 V.
The receiver threshold is less than +0/−70 mV. The receiver translates the differential Bus LVDS to standard (LVTTL/LVCMOS) levels. (See theApplication InformationSection for more details.)
The DS92LV040A is one in a series of Bus LVDS transceivers designed specifically for high speed, low power backplane or cable interfaces. The device operates from a single 3.3-V power supply and includes four differential line drivers and four receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.
The driver translates 3-V LVTTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation while consuming minimal power and reducing EMI. In addition, the differential signaling provides common mode noise rejection greater than ±1 V.
The receiver threshold is less than +0/−70 mV. The receiver translates the differential Bus LVDS to standard (LVTTL/LVCMOS) levels. (See theApplication InformationSection for more details.)
