CY74FCT821T Series

10-Bit Bus Interface Flip-Flops with 3-State Outputs

Catalog

10-Bit Bus Interface Flip-Flops with 3-State Outputs

Part	Number of Bits per Element	Current - Quiescent (Iq)	Package / Case	Package / Case [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Trigger Type	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Input Capacitance	Type	Function	Operating Temperature [Max]	Operating Temperature [Min]	Output Type	Max Propagation Delay @ V, Max CL	Number of Elements	Mounting Type	Package / Case [custom]	Package / Case	Package / Case
Texas Instruments CY74FCT821ATQCT	10	200 µA	24-SSOP	0.154 " 3.9 mm	64 mA	32 mA	Positive Edge	24-SSOP	4.75 V	5.25 V	5 pF	D-Type	Standard	85 °C	-40 °C	Non-Inverted Tri-State	6 ns	1	Surface Mount
Texas Instruments CY74FCT821ATSOCT	10	200 µA	24-SOIC	7.5 mm	64 mA	32 mA	Positive Edge	24-SOIC	4.75 V	5.25 V	5 pF	D-Type	Standard	85 °C	-40 °C	Non-Inverted Tri-State	20 ns	1	Surface Mount	0.295 in
Texas Instruments CY74FCT821ATSOC	10	200 µA	24-SOIC	7.5 mm	64 mA	32 mA	Positive Edge	24-SOIC	4.75 V	5.25 V	5 pF	D-Type	Standard	85 °C	-40 °C	Non-Inverted Tri-State	20 ns	1	Surface Mount	0.295 in
Texas Instruments CD74FCT821AEN
Texas Instruments CY74FCT821CTQC
Texas Instruments CY74FCT821CTSOC	10	200 µA	24-SOIC	7.5 mm	64 mA	32 mA	Positive Edge	24-SOIC	4.75 V	5.25 V	5 pF	D-Type	Standard	85 °C	-40 °C	Non-Inverted Tri-State	12.5 ns	1	Surface Mount	0.295 in
Texas Instruments CY74FCT821BTSOC	10	200 µA	24-SOIC	7.5 mm	64 mA	32 mA	Positive Edge	24-SOIC	4.75 V	5.25 V	5 pF	D-Type	Standard	85 °C	-40 °C	Non-Inverted Tri-State	15 ns	1	Surface Mount	0.295 in
Texas Instruments CY74FCT821BTPC	10	200 µA	24-DIP		64 mA	32 mA	Positive Edge	24-PDIP	4.75 V	5.25 V	5 pF	D-Type	Standard	85 °C	-40 °C	Non-Inverted Tri-State	6 ns	1	Through Hole		0.3 in	7.62 mm
Texas Instruments CY74FCT821BTSOCT	10	200 µA	24-SOIC	7.5 mm	64 mA	32 mA	Positive Edge	24-SOIC	4.75 V	5.25 V	5 pF	D-Type	Standard	85 °C	-40 °C	Non-Inverted Tri-State	15 ns	1	Surface Mount	0.295 in

Catalog

10-Bit Bus Interface Flip-Flops with 3-State Outputs

Key Features

• Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29821Reduced VOH(Typically = 3.3 V) Version of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)64-mA Output Sink Current32-mA Output Source CurrentHigh-Speed Parallel Register With Positive-Edge-Triggered D-Type Flip-Flops3-State OutputsFunction, Pinout, and Drive Compatible With FCT, F Logic, and AM29821Reduced VOH(Typically = 3.3 V) Version of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)64-mA Output Sink Current32-mA Output Source CurrentHigh-Speed Parallel Register With Positive-Edge-Triggered D-Type Flip-Flops3-State Outputs

Description

This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT821T is a 10-bit-wide buffered version of the popular CY74FCT374 function. This device is ideal for use as an output port requiring high IOL/IOH. This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT821T is a 10-bit-wide buffered version of the popular CY74FCT374 function. This device is ideal for use as an output port requiring high IOL/IOH. This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.