CDCM9102 Series

Low noise two channel 100-MHz PCIe clock generator

Catalog

Low noise two channel 100-MHz PCIe clock generator

Part	Mounting Type	Type	Ratio - Input:Output [custom]	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Input	Differential - Input:Output	PLL	Operating Temperature [Max]	Operating Temperature [Min]	Divider/Multiplier	Number of Circuits	Output	Package / Case
Texas Instruments CDCM9102RHBT	Surface Mount	Clock Generator	1:3	3.6 V	3 V	32-VQFN (5x5)	Crystal	No/Yes		85 °C	-40 °C		1	LVCMOS LVDS LVPECL	32-VFQFN Exposed Pad

Catalog

Low noise two channel 100-MHz PCIe clock generator

Key Features

• Integrated Low-Noise Clock Generator IncludingPLL, VCO, and Loop FilterTwo Low-Noise 100-MHz Clocks (LVPECL,LVDS, or pair of LVCMOS)Support for HCSL Signaling Levels(AC-Coupled)Typical Period Jitter: 21 ps pk-pkTypical Random Jitter: 510 fs RMSOutput Type Set by PinsBonus Single-Ended 25-MHz OutputIntegrated Crystal Oscillator Input Accepts25-MHz CrystalOutput Enable Pin Shuts Off Device and Outputs5-mm × 5-mm 32-Pin VQFN PackageESD Protection Exceeds 2000 V HBM, 500 VCDMIndustrial Temperature Range (–40°C to 85°C)3.3-V Power SupplyIntegrated Low-Noise Clock Generator IncludingPLL, VCO, and Loop FilterTwo Low-Noise 100-MHz Clocks (LVPECL,LVDS, or pair of LVCMOS)Support for HCSL Signaling Levels(AC-Coupled)Typical Period Jitter: 21 ps pk-pkTypical Random Jitter: 510 fs RMSOutput Type Set by PinsBonus Single-Ended 25-MHz OutputIntegrated Crystal Oscillator Input Accepts25-MHz CrystalOutput Enable Pin Shuts Off Device and Outputs5-mm × 5-mm 32-Pin VQFN PackageESD Protection Exceeds 2000 V HBM, 500 VCDMIndustrial Temperature Range (–40°C to 85°C)3.3-V Power Supply

Description

The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal. The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.