AM625SIP Series
General purpose system in package with Arm® Cortex®-A53 and integrated LPDDR4
Manufacturer: Texas Instruments
Catalog
General purpose system in package with Arm® Cortex®-A53 and integrated LPDDR4
Key Features
• Processor Cores:Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHzQuad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECCEach A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache withParity protectionSingle-core Arm® Cortex®-M4F MCU at up to400MHz256KB SRAM with SECDED ECCDedicated Device/Power ManagerMultimedia:Display subsystemDual display support1920x1080 @ 60fps for each display1x 2048x1080 + 1x 1280x720Up to 165MHz pixel clock support with Independent PLL for each displayOLDI (4 lanes LVDS - 2x) andDPI (24-bit RGB LVCMOS)Support safety feature such as freeze frame detection and MISR data check3D Graphics Processing Unit1 pixel per clock or higherFillrate greater than 500Mpixels/sec>500 MTexels/s, >8GFLOPsSupports at least 2 composition layersSupports up to 2048x1080 @60fpsSupports ARGB32, RGB565 and YUV formats2D graphics capableOpenGL ES 3.1, Vulkan 1.2One Camera Serial interface (CSI-Rx) - 4 Lane with DPHYMIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per laneECC verification/correction with CRC check + ECC on RAMVirtual Channel support (up to 16)Ability to write stream data directly to DDR via DMAMemory Subsystem:Up to 816KB of On-chip RAM64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks256KB of On-chip RAM with SECDED ECC in SMS Subsystem176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem64KB of On-chip RAM with SECDED ECC in Device/Power Manager SubsystemDDR Subsystem (DDRSS)Integrated 512MB LPDDR4 SDRAMSupports speeds up to 1600MT/s16-Bit data bus with inline ECCSecurity:Secure boot supportedHardware-enforced Root-of-Trust (RoT)Support to switch RoT via backup keySupport for takeover protection, IP protection, and anti-roll back protectionTrusted Execution Environment (TEE) supportedArm TrustZone based TEEExtensive firewall support for isolationSecure watchdog/timer/IPCSecure storage supportReplay Protected Memory Block (RPMB) supportDedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processingCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128-/192-/256-Bit key sizesSHA2 – 224-/256-/384-/512-Bit key sizesDRBG with true random number generatorPKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure bootDebugging securitySecure software controlled debug accessSecurity aware debuggingPRU Subsystem:Dual-core Programmable Real-Time Unit Subystem (PRUSS) running up to 333MHzIntended for driving GPIO for cycle accurate protocols such as additional:General Purpose Input/Output (GPIO)UARTsI2CExternal ADC16KByte program memory per PRU withSECDED ECC8KB data memory per PRU with SECDED ECC32KB general purpose memory withSECDED ECCCRC32/16 HW acceleratorScratch PAD memory with 3 banks of30 x 32-bit registers1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation1 interrupt controller (INTC), minimum of 64 input events supportedHigh-Speed Interfaces:Integrated Ethernet switch supporting(total of 2 external ports)RMII(10/100) or RGMII (10/100/1000)IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)Clause 45 MDIO PHY managementPacket Classifier based on ALE engine with 512 classifiersPriority based flow controlTime sensitive networking (TSN) supportFour CPU H/W interrupt PacingIP/UDP/TCP checksum offload in hardwareTwo USB2.0 PortsPort configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)Integrated USB VBUS detectionGeneral Connectivity:9x Universal Asynchronous Receiver-Transmitters (UART)5x Serial Peripheral Interface (SPI) controllers6x Inter-Integrated Circuit (I2C) ports3x Multichannel Audio Serial Ports (McASP)Transmit and Receive Clocks up to 50 MHzUp to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX ClocksSupports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar FormatsSupports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)FIFO Buffers for Transmit and Receive(256 Bytes)Support for audio reference output clock3x enhanced PWM modules (ePWM)3x enhanced Quadrature Encoder Pulse modules (eQEP)3x enhanced Capture modules (eCAP)General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO3x Controller Area Network (CAN) modules with CAN-FD supportConforms w/ CAN Protocol 2.0 A, B and ISO 11898-1Full CAN FD support (up to 64 data bytes)Parity/ECC check for Message RAMSpeed up to 8MbpsMedia and Data Storage:3x Multi-Media Card/Secure Digital(MMC/SD/SDIO) interface1x 8-bit eMMC interface up to HS200 speed2x 4-bit SD/SDIO interface up to UHS-ICompliant with eMMC 5.1, SD 3.0 andSDIO Version 3.01× General-Purpose Memory Controller (GPMC) up to 133 MHzFlexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)Uses BCH Code to Support 4-, 8-, or 16-Bit ECCUses Hamming Code to Support 1-Bit ECCError Locator Module (ELM)Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH AlgorithmSupports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH AlgorithmsOSPI/QSPI with DDR / SDR supportSupport for Serial NAND and Serial NOR flash devices4GBytes memory address supportXIP mode with optional on-the-fly encryptionPower Management:Low power modes supported by Device/Power ManagerPartial IO support for CAN/GPIO/UART wakeupDeepSleepMCU OnlyStandbyDynamic frequency scaling for Cortex-A53Optimal Power Management Solution:RecommendedTPS65219Power Management ICs (PMIC)Companion PMIC specially designed to meet device power supply requirementsFlexible mapping and factory programmed configurations to support different use casesBoot Options:UARTI2C EEPROMOSPI/QSPI FlashGPMC NOR/NAND FlashSerial NAND FlashSD CardeMMCUSB (host) boot from Mass Storage deviceUSB (device) boot from external host (DFU mode)EthernetTechnology / Package:16-nm technology13mm x 13mm, 0.5-mm pitch, 425-pinFCCSP BGA (AMK)Processor Cores:Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHzQuad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECCEach A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache withParity protectionSingle-core Arm® Cortex®-M4F MCU at up to400MHz256KB SRAM with SECDED ECCDedicated Device/Power ManagerMultimedia:Display subsystemDual display support1920x1080 @ 60fps for each display1x 2048x1080 + 1x 1280x720Up to 165MHz pixel clock support with Independent PLL for each displayOLDI (4 lanes LVDS - 2x) andDPI (24-bit RGB LVCMOS)Support safety feature such as freeze frame detection and MISR data check3D Graphics Processing Unit1 pixel per clock or higherFillrate greater than 500Mpixels/sec>500 MTexels/s, >8GFLOPsSupports at least 2 composition layersSupports up to 2048x1080 @60fpsSupports ARGB32, RGB565 and YUV formats2D graphics capableOpenGL ES 3.1, Vulkan 1.2One Camera Serial interface (CSI-Rx) - 4 Lane with DPHYMIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per laneECC verification/correction with CRC check + ECC on RAMVirtual Channel support (up to 16)Ability to write stream data directly to DDR via DMAMemory Subsystem:Up to 816KB of On-chip RAM64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks256KB of On-chip RAM with SECDED ECC in SMS Subsystem176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem64KB of On-chip RAM with SECDED ECC in Device/Power Manager SubsystemDDR Subsystem (DDRSS)Integrated 512MB LPDDR4 SDRAMSupports speeds up to 1600MT/s16-Bit data bus with inline ECCSecurity:Secure boot supportedHardware-enforced Root-of-Trust (RoT)Support to switch RoT via backup keySupport for takeover protection, IP protection, and anti-roll back protectionTrusted Execution Environment (TEE) supportedArm TrustZone based TEEExtensive firewall support for isolationSecure watchdog/timer/IPCSecure storage supportReplay Protected Memory Block (RPMB) supportDedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processingCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128-/192-/256-Bit key sizesSHA2 – 224-/256-/384-/512-Bit key sizesDRBG with true random number generatorPKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure bootDebugging securitySecure software controlled debug accessSecurity aware debuggingPRU Subsystem:Dual-core Programmable Real-Time Unit Subystem (PRUSS) running up to 333MHzIntended for driving GPIO for cycle accurate protocols such as additional:General Purpose Input/Output (GPIO)UARTsI2CExternal ADC16KByte program memory per PRU withSECDED ECC8KB data memory per PRU with SECDED ECC32KB general purpose memory withSECDED ECCCRC32/16 HW acceleratorScratch PAD memory with 3 banks of30 x 32-bit registers1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation1 interrupt controller (INTC), minimum of 64 input events supportedHigh-Speed Interfaces:Integrated Ethernet switch supporting(total of 2 external ports)RMII(10/100) or RGMII (10/100/1000)IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)Clause 45 MDIO PHY managementPacket Classifier based on ALE engine with 512 classifiersPriority based flow controlTime sensitive networking (TSN) supportFour CPU H/W interrupt PacingIP/UDP/TCP checksum offload in hardwareTwo USB2.0 PortsPort configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)Integrated USB VBUS detectionGeneral Connectivity:9x Universal Asynchronous Receiver-Transmitters (UART)5x Serial Peripheral Interface (SPI) controllers6x Inter-Integrated Circuit (I2C) ports3x Multichannel Audio Serial Ports (McASP)Transmit and Receive Clocks up to 50 MHzUp to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX ClocksSupports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar FormatsSupports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)FIFO Buffers for Transmit and Receive(256 Bytes)Support for audio reference output clock3x enhanced PWM modules (ePWM)3x enhanced Quadrature Encoder Pulse modules (eQEP)3x enhanced Capture modules (eCAP)General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO3x Controller Area Network (CAN) modules with CAN-FD supportConforms w/ CAN Protocol 2.0 A, B and ISO 11898-1Full CAN FD support (up to 64 data bytes)Parity/ECC check for Message RAMSpeed up to 8MbpsMedia and Data Storage:3x Multi-Media Card/Secure Digital(MMC/SD/SDIO) interface1x 8-bit eMMC interface up to HS200 speed2x 4-bit SD/SDIO interface up to UHS-ICompliant with eMMC 5.1, SD 3.0 andSDIO Version 3.01× General-Purpose Memory Controller (GPMC) up to 133 MHzFlexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)Uses BCH Code to Support 4-, 8-, or 16-Bit ECCUses Hamming Code to Support 1-Bit ECCError Locator Module (ELM)Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH AlgorithmSupports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH AlgorithmsOSPI/QSPI with DDR / SDR supportSupport for Serial NAND and Serial NOR flash devices4GBytes memory address supportXIP mode with optional on-the-fly encryptionPower Management:Low power modes supported by Device/Power ManagerPartial IO support for CAN/GPIO/UART wakeupDeepSleepMCU OnlyStandbyDynamic frequency scaling for Cortex-A53Optimal Power Management Solution:RecommendedTPS65219Power Management ICs (PMIC)Companion PMIC specially designed to meet device power supply requirementsFlexible mapping and factory programmed configurations to support different use casesBoot Options:UARTI2C EEPROMOSPI/QSPI FlashGPMC NOR/NAND FlashSerial NAND FlashSD CardeMMCUSB (host) boot from Mass Storage deviceUSB (device) boot from external host (DFU mode)EthernetTechnology / Package:16-nm technology13mm x 13mm, 0.5-mm pitch, 425-pinFCCSP BGA (AMK)
Description
AI
AM625SIP is a System In Package (SIP) derivative of the ALW packaged AM6254 device, with the addition of an integrated LPDDR4 SDRAM. This document only defines differences or exceptions to the ALW packaged AM6254 device defined inAM62x Sitara Processors Datasheet(revision B or later).
The AM625SIP (System in Package) Sitara™ MPU with integrated LPDDR4 is an application processor built for Linux development. The system in package integrates 512MB of LPDDR4 with the AM6254 device which has 4x Arm® Cortex®-A53 performance and embedded features, such as: dual-display support, 3D graphics acceleration, along with an extensive set of peripherals that make the System in package well-suited for a broad range of industrial applications while offering intelligent features and optimized power architecture. Additionally, the AM625SIP offers a simplified hardware design, increased robustness, optimized size/system BOM, and power consumption savings all enabling faster software and hardware development.
Some of these applications include:
The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) support. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM625SIP enables system-level connectivity, such as: USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM625SIP device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications
AM625SIP is a System In Package (SIP) derivative of the ALW packaged AM6254 device, with the addition of an integrated LPDDR4 SDRAM. This document only defines differences or exceptions to the ALW packaged AM6254 device defined inAM62x Sitara Processors Datasheet(revision B or later).
The AM625SIP (System in Package) Sitara™ MPU with integrated LPDDR4 is an application processor built for Linux development. The system in package integrates 512MB of LPDDR4 with the AM6254 device which has 4x Arm® Cortex®-A53 performance and embedded features, such as: dual-display support, 3D graphics acceleration, along with an extensive set of peripherals that make the System in package well-suited for a broad range of industrial applications while offering intelligent features and optimized power architecture. Additionally, the AM625SIP offers a simplified hardware design, increased robustness, optimized size/system BOM, and power consumption savings all enabling faster software and hardware development.
Some of these applications include:
The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) support. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM625SIP enables system-level connectivity, such as: USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM625SIP device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications