ADC09SJ800 Series

Single-channel, 9-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface

Catalog

Single-channel, 9-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface

Part	Data Interface	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Number of Bits	Operating Temperature [Max]	Operating Temperature [Min]	Input Type	Architecture	Configuration	Sampling Rate (Per Second)	Ratio - S/H:ADC	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Mounting Type	Package / Case	Supplier Device Package	Number of Inputs	Number of A/D Converters
Texas Instruments ADC09SJ800AAVT	JESD204C Serial	1.05 V 1.8 V	1.15 V 2 V	9	85 °C	-40 °C	Differential	Pipelined SAR	ADC	800 M	0:1	1.15 V	1.05 V	Surface Mount	144-FBGA FCBGA	144-FCBGA (10x10)	1	1
Texas Instruments ADC09SJ800AAV	JESD204C Serial	1.05 V 1.8 V	1.15 V 2 V	9	125 °C	-40 °C	Differential	Pipelined SAR	ADC	800 M		1.15 V	1.05 V	Surface Mount	144-FBGA FCBGA	144-FCBGA (10x10)	1	1

Catalog

Single-channel, 9-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface

Key Features

• ADC Core:Resolution: 9 BitNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications:SNR (–1dBFS, 97MHz): 53.5dBFSENOB (–1dBFS, 97MHz): 8.51BitsSFDR (–1dBFS, 97MHz): 64dBFSNoise floor (–20dBFS, 97MHz): –140.5dBFS/HzFull-scale input voltage: 800mVPP-DIFFFull-power input bandwidth: 6GHzJESD204C Serial data interface:Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2 GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (800 MSPS):Quad Channel: 420mW / channelDual channel: 555mW / channelSingle channel: 840mWPower supplies: 1.1V, 1.9VADC Core:Resolution: 9 BitNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications:SNR (–1dBFS, 97MHz): 53.5dBFSENOB (–1dBFS, 97MHz): 8.51BitsSFDR (–1dBFS, 97MHz): 64dBFSNoise floor (–20dBFS, 97MHz): –140.5dBFS/HzFull-scale input voltage: 800mVPP-DIFFFull-power input bandwidth: 6GHzJESD204C Serial data interface:Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2 GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (800 MSPS):Quad Channel: 420mW / channelDual channel: 555mW / channelSingle channel: 840mWPower supplies: 1.1V, 1.9V

Description

ADC09xJ800 is a family of quad, dual and single channel, 9-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC09xJ800 ideally suited for a variety of multichannel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. ADC09xJ800 is a family of quad, dual and single channel, 9-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC09xJ800 ideally suited for a variety of multichannel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.