Catalog
High-speed differential line receivers
Key Features
• Eight Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 StandardIntegrated 110-Line Termination Resistors on LVDT ProductsDesigned for Signaling RatesUp To 630 MbpsSN65 Version's Bus-Terminal ESD Exceeds 15 kVOperates From a Single 3.3-V SupplyPropagation Delay Time of 2.6 ns (Typ)Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 nsLVTTL Levels Are 5-V TolerantOpen-Circuit Fail SafeFlow-Through Pin OutPackaged in Thin Shrink Small-Outline Package With 20-mil Terminal PitchSignaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)Eight Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 StandardIntegrated 110-Line Termination Resistors on LVDT ProductsDesigned for Signaling RatesUp To 630 MbpsSN65 Version's Bus-Terminal ESD Exceeds 15 kVOperates From a Single 3.3-V SupplyPropagation Delay Time of 2.6 ns (Typ)Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 nsLVTTL Levels Are 5-V TolerantOpen-Circuit Fail SafeFlow-Through Pin OutPackaged in Thin Shrink Small-Outline Package With 20-mil Terminal PitchSignaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
Description
AI
The \x91LVDS388 and \x91LVDT388 (Tdesignates integrated termination) are eight differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight differential receivers will provide a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals always require the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT product eliminates this external resistor by integrating it with the receiver.
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, 8-channel driver, the SN65LVDS389 over 150 million data transfers per second in single-edge clocked systems are possible with very little power. Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.
The SN65LVDS388 and SN65LVDT388 is characterized for operation from -40°C to 85°C. The SN75LVDS388 and SN75LVDT388 is characterized for operation from 0°C to 70°C.
The \x91LVDS388 and \x91LVDT388 (Tdesignates integrated termination) are eight differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight differential receivers will provide a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals always require the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT product eliminates this external resistor by integrating it with the receiver.
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, 8-channel driver, the SN65LVDS389 over 150 million data transfers per second in single-edge clocked systems are possible with very little power. Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.
The SN65LVDS388 and SN65LVDT388 is characterized for operation from -40°C to 85°C. The SN75LVDS388 and SN75LVDT388 is characterized for operation from 0°C to 70°C.
