SM320C6701 Series
Single core C67x floating-point DSP for military applications - up to 167MHz
Manufacturer: Texas Instruments
Catalog
Single core C67x floating-point DSP for military applications - up to 167MHz
| Part | Voltage - I/O | Mounting Type | Clock Rate | Package / Case | Operating Temperature [Min] | Operating Temperature [Max] | Interface | Type | On-Chip RAM | Voltage - Core | Non-Volatile Memory | Supplier Device Package |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments | 3.3 V | Surface Mount | 140 MHz | 429-BCBGA FCBGA | -55 °C | 115 °C | DMA EMIF HPI McBSP SPI | Floating Point | 128 kB | 1.9 V | 128 kB | 429-CFCBGA (27x27) |
Texas Instruments | 3.3 V | Surface Mount | 167 MHz | 429-BCBGA FCBGA | -40 °C | 90 °C | DMA EMIF HPI McBSP SPI | Floating Point | 128 kB | 1.9 V | 128 kB | 429-CFCBGA (27x27) |
Key Features
• Highest Performance Floating-Point DigitalSignal Processor (DSP) SMJ320C67017-, 6-ns Instruction Cycle Time140-, 167-MHz Clock RateEight 32-Bit Instructions/CycleUp to 1 GFLOPS PerformancePin-Compatible With ’C6201 Fixed-Point DSPSMJ: QML Processing to MIL-PRF-38535SM: Standard ProcessingOperating Temperature RangesExtended (W) –55°C to 115°CExtended (S) –40°C to 90°CVelociTI™ Advanced Very Long InstructionWord (VLIW) ’C67x CPU CoreEight Highly Independent Functional Units:Four ALUs (Floating- and Fixed-Point)Two ALUs (Fixed-Point)Two Multipliers (Floating- andFixed-Point)Load-Store Architecture With 32 32-BitGeneral-Purpose RegistersInstruction Packing Reduces Code SizeAll Instructions ConditionalInstruction Set FeaturesHardware Support for IEEESingle-Precision InstructionsHardware Support for IEEEDouble-Precision InstructionsByte-Addressable (8-, 16-, 32-Bit Data)32-Bit Address Range8-Bit Overflow ProtectionSaturationBit-Field Extract, Set, ClearBit-CountingNormalization1M-Bit On-Chip SRAM512K-Bit Internal Program/Cache(16K 32-Bit Instructions)512K-Bit Dual-Access Internal Data(64K Bytes)32-Bit External Memory Interface (EMIF)Glueless Interface to SynchronousMemories: SDRAM and SBSRAMGlueless Interface to AsynchronousMemories: SRAM and EPROMFour-Channel BootloadingDirect-Memory-Access (DMA) ControllerWith an Auxiliary Channel16-Bit Host-Port Interface (HPI)Access to Entire Memory MapTwo Multichannel Buffered Serial Ports(McBSPs)Direct Interface to T1/E1, MVIP, SCSAFramersST-Bus-Switching CompatibleUp to 256 Channels EachAC97-CompatibleSerial-Peripheral-Interface (SPI)Compatible (Motorola™)Two 32-Bit General-Purpose TimersFlexible Phase-Locked-Loop (PLL) ClockGeneratorIEEE-1149.1 (JTAG)Boundary-Scan-Compatible429-Pin Ceramic Ball Grid Array (CBGA)Package (GLP Suffix) and Land Grid Array(CLGA) Package (ZMB Suffix)0.18-µm/5-Level Metal ProcessCMOS Technology3.3-V I/Os, 1.9-V InternalIEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.VelociTI is a trademark of Texas Instruments Incorporated.Motorola is a trademark of Motorola, Inc.TI is a trademark of Texas Instruments Incorporated.Windows is a registered trademark of the Microsoft Corporation.Highest Performance Floating-Point DigitalSignal Processor (DSP) SMJ320C67017-, 6-ns Instruction Cycle Time140-, 167-MHz Clock RateEight 32-Bit Instructions/CycleUp to 1 GFLOPS PerformancePin-Compatible With ’C6201 Fixed-Point DSPSMJ: QML Processing to MIL-PRF-38535SM: Standard ProcessingOperating Temperature RangesExtended (W) –55°C to 115°CExtended (S) –40°C to 90°CVelociTI™ Advanced Very Long InstructionWord (VLIW) ’C67x CPU CoreEight Highly Independent Functional Units:Four ALUs (Floating- and Fixed-Point)Two ALUs (Fixed-Point)Two Multipliers (Floating- andFixed-Point)Load-Store Architecture With 32 32-BitGeneral-Purpose RegistersInstruction Packing Reduces Code SizeAll Instructions ConditionalInstruction Set FeaturesHardware Support for IEEESingle-Precision InstructionsHardware Support for IEEEDouble-Precision InstructionsByte-Addressable (8-, 16-, 32-Bit Data)32-Bit Address Range8-Bit Overflow ProtectionSaturationBit-Field Extract, Set, ClearBit-CountingNormalization1M-Bit On-Chip SRAM512K-Bit Internal Program/Cache(16K 32-Bit Instructions)512K-Bit Dual-Access Internal Data(64K Bytes)32-Bit External Memory Interface (EMIF)Glueless Interface to SynchronousMemories: SDRAM and SBSRAMGlueless Interface to AsynchronousMemories: SRAM and EPROMFour-Channel BootloadingDirect-Memory-Access (DMA) ControllerWith an Auxiliary Channel16-Bit Host-Port Interface (HPI)Access to Entire Memory MapTwo Multichannel Buffered Serial Ports(McBSPs)Direct Interface to T1/E1, MVIP, SCSAFramersST-Bus-Switching CompatibleUp to 256 Channels EachAC97-CompatibleSerial-Peripheral-Interface (SPI)Compatible (Motorola™)Two 32-Bit General-Purpose TimersFlexible Phase-Locked-Loop (PLL) ClockGeneratorIEEE-1149.1 (JTAG)Boundary-Scan-Compatible429-Pin Ceramic Ball Grid Array (CBGA)Package (GLP Suffix) and Land Grid Array(CLGA) Package (ZMB Suffix)0.18-µm/5-Level Metal ProcessCMOS Technology3.3-V I/Os, 1.9-V InternalIEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.VelociTI is a trademark of Texas Instruments Incorporated.Motorola is a trademark of Motorola, Inc.TI is a trademark of Texas Instruments Incorporated.Windows is a registered trademark of the Microsoft Corporation.
Description
AI
The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI™), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.
The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI™), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.