Catalog
CMOS 18-Stage Static Shift Register
Key Features
• Fully static operationShifting rates up to 12 MHz @ 10 V (typ.)Permanent register storage with clock line high or low - no information recirculation required100% tested for quiescent current at 20 VStandardized, symmetrical output characteristics5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (full package-temperature range) =1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' series CMOS Devices"ApplicationsSerial shift registersFrequency divisionTime delay circuitsFully static operationShifting rates up to 12 MHz @ 10 V (typ.)Permanent register storage with clock line high or low - no information recirculation required100% tested for quiescent current at 20 VStandardized, symmetrical output characteristics5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (full package-temperature range) =1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' series CMOS Devices"ApplicationsSerial shift registersFrequency divisionTime delay circuits
Description
AI
CD4006B types are composed of 4 separate shift register sections: two sections of four stages and two sections of five stages with an output tap at the fourth stage. Each section has an independent single-rail data path.
A common clock signal is used for all stages. Data are shifted to the next stage on negative-going transitions of the clock. Through appropriate connections of inputs and outputs, multiple register sections of 4, 5, 8, and 9 stages or single register sections of 10, 12, 13, 14, 16, 17 and 18 stages can be implemented using one CD4006B package. Longer shift register sections can be assembled by using more than one CD4006B.
To facilitate cascading stages when clock rise and fall times are slow, an optional output (D1+4') that is delayed one-half clock-cycle, is provided (see Truth Table for Output from Term. 2).
The CD4006B types are supplied in 14-lead hermetic dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
CD4006B types are composed of 4 separate shift register sections: two sections of four stages and two sections of five stages with an output tap at the fourth stage. Each section has an independent single-rail data path.
A common clock signal is used for all stages. Data are shifted to the next stage on negative-going transitions of the clock. Through appropriate connections of inputs and outputs, multiple register sections of 4, 5, 8, and 9 stages or single register sections of 10, 12, 13, 14, 16, 17 and 18 stages can be implemented using one CD4006B package. Longer shift register sections can be assembled by using more than one CD4006B.
To facilitate cascading stages when clock rise and fall times are slow, an optional output (D1+4') that is delayed one-half clock-cycle, is provided (see Truth Table for Output from Term. 2).
The CD4006B types are supplied in 14-lead hermetic dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
