MC100EP196 Series

3.3 V ECL Programmable Delay Chip

Catalog

3.3 V ECL Programmable Delay Chip

Part	Mounting Type	Number of Independent Delays	Supplier Device Package	Function	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Delay to 1st Tap	Operating Temperature [Max]	Operating Temperature [Min]	Number of Taps/Steps	Tap Increment	Available Total Delays [Min]	Available Total Delays [Max]
ON Semiconductor MC100EP196FAR2	Surface Mount	1	32-LQFP (7x7)	Programmable	32-LQFP	3.6 V	3 V	2.36 ns	85 °C	-40 °C	1024	10 ps	2.36 ns	12.258 ns

Catalog

3.3 V ECL Programmable Delay Chip

Key Features

• Maximum Frequency > 1.2 GHz Typical

• PECL Mode Operating Range: VCC= 3.0 V to 3.6 V with VEE= 0 V

• NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.6 V

• Open Input Default State

• Safety Clamp on Inputs

• A Logic High on the ENbar Pin Will Force Q to Logic Low

• D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs

• VBBOutput Reference Voltage

• Pb-Free Packages are Available

Description

The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCCto VEEto fine tune the output delay from 0 to 60 ps.