SN74AHCT139-Q1 Series
Automotive dual 2-line to 4-line decoders or demultiplexers with TTL inputs
Manufacturer: Texas Instruments
Catalog
Automotive dual 2-line to 4-line decoders or demultiplexers with TTL inputs
Key Features
• AEC-Q100 qualified for automotive applications:Device temperature grade 1: -40°C to +125°CDevice HBM ESD classification level 2Device CDM ESD classification level C4BAvailable in wettable flank QFN packageOperating range 4.5V to 5.5V VCCTTL-Compatible inputsLow delay, 9.6ns max (VCC = 5V, CL = 50pFLatch-up performance exceeds 250mAper JESD 17AEC-Q100 qualified for automotive applications:Device temperature grade 1: -40°C to +125°CDevice HBM ESD classification level 2Device CDM ESD classification level C4BAvailable in wettable flank QFN packageOperating range 4.5V to 5.5V VCCTTL-Compatible inputsLow delay, 9.6ns max (VCC = 5V, CL = 50pFLatch-up performance exceeds 250mAper JESD 17
Description
AI
The SN74AHCT139-Q1 contains two 2-line to 4-line decoders/demultiplexers. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The SN74AHCT139-Q1 contains two 2-line to 4-line decoders/demultiplexers. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.