SN74AUC126 Series

4-ch, 0.8-V to 2.7-V high speed buffers with 3-state outputs

Catalog

4-ch, 0.8-V to 2.7-V high speed buffers with 3-state outputs

Part	Logic Type	Number of Elements	Number of Bits per Element	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Output Type	Package / Case	Supplier Device Package
Texas Instruments SN74AUC126RGYR	Buffer Non-Inverting	4	1	2.7 V	0.8 V	Surface Mount	9 mA	9 mA	85 °C	-40 °C	3-State	14-VFQFN Exposed Pad	14-VQFN (3.5x3.5)

Catalog

4-ch, 0.8-V to 2.7-V high speed buffers with 3-state outputs

Key Features

• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub 1-V OperableMax tpdof 2.1 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1500-V Charged-Device Model (C101)Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub 1-V OperableMax tpdof 2.1 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1500-V Charged-Device Model (C101)

Description

This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCCoperation, but is designed specifically for 1.6-V to 1.95-V VCCoperation. The SN74AUC126 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCCoperation, but is designed specifically for 1.6-V to 1.95-V VCCoperation. The SN74AUC126 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.