ADC09DJ1300 Series

Dual-channel, 9-bit, 1.3-GSPS analog-to-digital converter (ADC) with JESD204C interface

Catalog

Dual-channel, 9-bit, 1.3-GSPS analog-to-digital converter (ADC) with JESD204C interface

Part	Configuration	Number of A/D Converters	Operating Temperature [Max]	Operating Temperature [Min]	Number of Inputs	Supplier Device Package	Data Interface	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Input Type	Ratio - S/H:ADC	Number of Bits	Mounting Type	Sampling Rate (Per Second)	Package / Case	Architecture	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]
Texas Instruments ADC09DJ1300AAVT	ADC	2	85 °C	-40 °C	2	144-FCBGA (10x10)	JESD204C Serial	1.15 V	1.05 V	Differential	0:2	9	Surface Mount	1.3 G	144-FBGA FCBGA	Pipelined SAR	1.05 V 1.8 V	1.15 V 2 V
Texas Instruments ADC09DJ1300AAV	ADC	2	85 °C	-40 °C	2	144-FCBGA (10x10)	JESD204C Serial	1.15 V	1.05 V	Differential		9	Surface Mount	1.3 G	144-FBGA FCBGA	Pipelined SAR	1.05 V 1.8 V	1.15 V 2 V

Catalog

Dual-channel, 9-bit, 1.3-GSPS analog-to-digital converter (ADC) with JESD204C interface

Key Features

• ADC Core:Resolution: 9 BitMaximum sampling rate: 1.3GSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1dBFS):SNR (100 MHz): 53.5dBFSENOB (100 MHz): 8.5 BitsSFDR (100 MHz): 64dBcNoise floor (–20dBFS): –143dBFSFull-scale input voltage: 80 mVPP-DIFFFull-power input bandwidth: 6GHzJESD204C Serial data interface:Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (1GSPS):Quad Channel: 450mW / channelDual channel: 625mW / channelSingle channel: 940mWPower supplies: 1.1V, 1.9VADC Core:Resolution: 9 BitMaximum sampling rate: 1.3GSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1dBFS):SNR (100 MHz): 53.5dBFSENOB (100 MHz): 8.5 BitsSFDR (100 MHz): 64dBcNoise floor (–20dBFS): –143dBFSFull-scale input voltage: 80 mVPP-DIFFFull-power input bandwidth: 6GHzJESD204C Serial data interface:Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (1GSPS):Quad Channel: 450mW / channelDual channel: 625mW / channelSingle channel: 940mWPower supplies: 1.1V, 1.9V

Description

ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.