LMX1204 Series
12.8-GHz RF buffer, multiplier and divider with JESD204B/C SYSREF support and phase synchronization
Manufacturer: Texas Instruments
Catalog
12.8-GHz RF buffer, multiplier and divider with JESD204B/C SYSREF support and phase synchronization
Key Features
• 300MHz to 12.8GHz output frequencyUltra-low noiseNoise floor of –161dBc/Hz at 6GHz output1/f Noise of –154dBc/Hz at 6GHz output, 10kHz offset5fs jitter (12kHz to 20MHz)<30fs additive jitter (DC to fCLK )4 high-frequency clocks with corresponding SYSREF outputsShared divider that supports ÷1 (buffer mode), ÷2, 3, 4, 5, 6, 7, and 8Shared PLL-based multiplier that supports x1 (filter mode), x2, x3, and x4LOGICLK and corresponding SYSREF outputsOn separate divide bank÷1, 2, 4 pre-divider÷1 (bypass), 2, …, 1023 post divider8 programmable output power levelsSynchronized SYSREF clock outputs508 delay step adjustments of less than 2.5ps each at 12.8GHzGenerator and repeater modesWindowing feature for SYSREFREQ pins to optimize timingSYNC feature to all divides and multiple devices2.5V operating voltage–40ºC to 85ºC operating temperature300MHz to 12.8GHz output frequencyUltra-low noiseNoise floor of –161dBc/Hz at 6GHz output1/f Noise of –154dBc/Hz at 6GHz output, 10kHz offset5fs jitter (12kHz to 20MHz)<30fs additive jitter (DC to fCLK )4 high-frequency clocks with corresponding SYSREF outputsShared divider that supports ÷1 (buffer mode), ÷2, 3, 4, 5, 6, 7, and 8Shared PLL-based multiplier that supports x1 (filter mode), x2, x3, and x4LOGICLK and corresponding SYSREF outputsOn separate divide bank÷1, 2, 4 pre-divider÷1 (bypass), 2, …, 1023 post divider8 programmable output power levelsSynchronized SYSREF clock outputs508 delay step adjustments of less than 2.5ps each at 12.8GHzGenerator and repeater modesWindowing feature for SYSREFREQ pins to optimize timingSYNC feature to all divides and multiple devices2.5V operating voltage–40ºC to 85ºC operating temperature
Description
AI
The high-frequency capability and extremely low jitter of this device, makes a great approach to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the four high-frequency clock outputs, and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, having the jitter of the clock be less than the aperture jitter of the data converter is critical. In applications where more than four data converters must be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high-frequency clocks and SYSREF signals required. With low jitter and noise floor, this device combined with an ultra-low noise reference clock source is an exemplary selection for clocking data converters, especially when sampling above 3GHz.
The high-frequency capability and extremely low jitter of this device, makes a great approach to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the four high-frequency clock outputs, and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, having the jitter of the clock be less than the aperture jitter of the data converter is critical. In applications where more than four data converters must be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high-frequency clocks and SYSREF signals required. With low jitter and noise floor, this device combined with an ultra-low noise reference clock source is an exemplary selection for clocking data converters, especially when sampling above 3GHz.
