SN74LV4046A Series

High-Speed CMOS Logic Phase-Locked Loop with VCO

Catalog

High-Speed CMOS Logic Phase-Locked Loop with VCO

Part	Operating Temperature [Max]	Operating Temperature [Min]	Type	Package / Case	Package / Case	Package / Case	Frequency - Max [Max]	Ratio - Input:Output [custom]	Number of Circuits	Input	Output	Supplier Device Package	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case [y]	Package / Case [x]
Texas Instruments SN74LV4046ANSR	125 °C	-40 °C	Phase Lock Loop (PLL)	0.209 "	16-SOIC	5.3 mm	38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-SO	Surface Mount	5.5 V	3 V
Texas Instruments SN74LV4046AN	125 °C	-40 °C	Phase Lock Loop (PLL)	0.3 in	16-DIP	7.62 mm	38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-PDIP	Through Hole	5.5 V	3 V
Texas Instruments SN74LV4046ADGVR	125 °C	-40 °C	Phase Lock Loop (PLL)		16-TFSOP		38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-TVSOP	Surface Mount	5.5 V	3 V	4.4 mm	0.173 in
Texas Instruments SN74LV4046APWG4	125 °C	-40 °C	Phase Lock Loop (PLL)		16-TSSOP		38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-TSSOP	Surface Mount	5.5 V	3 V	4.4 mm	0.173 in
Texas Instruments SN74LV4046ANG4	125 °C	-40 °C	Phase Lock Loop (PLL)	0.3 in	16-DIP	7.62 mm	38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-PDIP	Through Hole	5.5 V	3 V
Texas Instruments SN74LV4046AD	125 °C	-40 °C	Phase Lock Loop (PLL)		16-SOIC		38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-SOIC	Surface Mount	5.5 V	3 V	3.9 mm	0.154 in
Texas Instruments SN74LV4046ANS	125 °C	-40 °C	Phase Lock Loop (PLL)	0.209 "	16-SOIC	5.3 mm	38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-SO	Surface Mount	5.5 V	3 V
Texas Instruments SN74LV4046APWR	125 °C	-40 °C	Phase Lock Loop (PLL)		16-TSSOP		38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-TSSOP	Surface Mount	5.5 V	3 V	4.4 mm	0.173 in
Texas Instruments SN74LV4046ADR	125 °C	-40 °C	Phase Lock Loop (PLL)		16-SOIC		38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-SOIC	Surface Mount	5.5 V	3 V	3.9 mm	0.154 in
Texas Instruments SN74LV4046APW	125 °C	-40 °C	Phase Lock Loop (PLL)		16-TSSOP		38 MHz	1:3	1	CMOS TTL	CMOS TTL	16-TSSOP	Surface Mount	5.5 V	3 V	4.4 mm	0.173 in

Catalog

High-Speed CMOS Logic Phase-Locked Loop with VCO

Key Features

• ESD Protection Exceeds JESD 222000-V Human Body Model (A114-A)1000-V Charged-Device Model (C101)Choice of Three Phase ComparatorsExclusive OREdge-Triggered J-K Flip-FlopEdge-Triggered RS Flip-FlopExcellent VCO Frequency LinearityVCO-Inhibit Control for ON/OFF Keying and for Low Standby Power ConsumptionOptimized Power-Supply Voltage Range From 3 V to 5.5 VWide Operating Temperature Range From –40°C to +125°CLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human Body Model (A114-A)1000-V Charged-Device Model (C101)Choice of Three Phase ComparatorsExclusive OREdge-Triggered J-K Flip-FlopEdge-Triggered RS Flip-FlopExcellent VCO Frequency LinearityVCO-Inhibit Control for ON/OFF Keying and for Low Standby Power ConsumptionOptimized Power-Supply Voltage Range From 3 V to 5.5 VWide Operating Temperature Range From –40°C to +125°CLatch-Up Performance Exceeds 250 mA Per JESD 17

Description

The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7. The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators. The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7. The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators.