Catalog
Low-jitter dual-channel network synchronizer clock
Key Features
• Two Independent PLL Channels Featuring:Jitter: 150fs RMS for Outputs ≥ 100MHzPhase Noise: –112dBc/Hz at 100Hz Offset for 122.88MHzHitless Switching: 50ps Phase Transient With Phase CancellationProgrammable Loop Bandwidth With FastlockStandards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXOAny Input to Any Output Frequency TranslationFour Reference Clock InputsPriority-Based Input SelectionDigital Holdover on Loss of ReferenceEight Clock Outputs With Programmable DriversUp to Six Different Output FrequenciesAC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8V or 2.5V LVCMOS Output FormatsEEPROM/ROM for Custom Clocks on Power-UpFlexible Configuration OptionsUp to 750MHz on Input and OutputXO: 10MHz to 100MHz, TCXO: 10MHz to 54MHzDCO Mode: < 1ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave)Zero Delay for Deterministic Phase OffsetRobust Clock Monitoring and StatusI2C or SPI InterfaceExcellent Power Supply Noise Rejection (PSNR)3.3V Supply With 1.8V, 2.5V, or 3.3V OutputsIndustrial Temperature Range: –40°C to +85°CTwo Independent PLL Channels Featuring:Jitter: 150fs RMS for Outputs ≥ 100MHzPhase Noise: –112dBc/Hz at 100Hz Offset for 122.88MHzHitless Switching: 50ps Phase Transient With Phase CancellationProgrammable Loop Bandwidth With FastlockStandards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXOAny Input to Any Output Frequency TranslationFour Reference Clock InputsPriority-Based Input SelectionDigital Holdover on Loss of ReferenceEight Clock Outputs With Programmable DriversUp to Six Different Output FrequenciesAC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8V or 2.5V LVCMOS Output FormatsEEPROM/ROM for Custom Clocks on Power-UpFlexible Configuration OptionsUp to 750MHz on Input and OutputXO: 10MHz to 100MHz, TCXO: 10MHz to 54MHzDCO Mode: < 1ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave)Zero Delay for Deterministic Phase OffsetRobust Clock Monitoring and StatusI2C or SPI InterfaceExcellent Power Supply Noise Rejection (PSNR)3.3V Supply With 1.8V, 2.5V, or 3.3V OutputsIndustrial Temperature Range: –40°C to +85°C
Description
AI
The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and good hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The low jitter and high PSNR of the device reduce bit error rates (BER) in high-speed serial links.
The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize the outputs.
The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and good hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The low jitter and high PSNR of the device reduce bit error rates (BER) in high-speed serial links.
The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize the outputs.
