ADS58J64 Series

Quad-channel, 14-bit, 1-GSPS telecom receiver and feedback IC

Catalog

Quad-channel, 14-bit, 1-GSPS telecom receiver and feedback IC

Part	Package / Case	Sampling Rate (Per Second)	Resolution (Bits)	Voltage - Supply [Min]	Voltage - Supply [Max]	Voltage Supply Source	Supplier Device Package	Type	Number of Channels	Operating Temperature [Max]	Operating Temperature [Min]	Data Interface	Mounting Type
Texas Instruments ADS58J64IRMPT	72-VFQFN Exposed Pad	500 M	14 b	1.1 V 1.8 V	1.2 V 2 V	Analog and Digital	72-VQFN (10x10)	Capacitance-to-Digital Converter	4	85 °C	-40 °C	JESD204B	Surface Mount
Texas Instruments ADS58J64IRRHR	72-VFQFN Exposed Pad	1 G	14 b	1.1 V 1.8 V	1.2 V 2 V	Analog and Digital	72-VQFN (10x10)	Capacitance-to-Digital Converter	4	85 °C	-40 °C	JESD204B	Surface Mount

Catalog

Quad-channel, 14-bit, 1-GSPS telecom receiver and feedback IC

Key Features

• Quad Channel14-Bit ResolutionMaximum Sampling Rate: 1 GSPSMaximum Output Sample Rate: 500 MSPSAnalog Input Buffer With High-Impedance InputInput 3-dB Bandwidth: 1 GHzOutput Options:Rx: Decimate-by-2 and -4 Options With Low-Pass Filter200-MHz Complex Bandwidth or 100-MHz Real Bandwidth SupportDPD FB: 2x Decimation With 14-Bit Burst Mode Output1.1-VPPDifferential Full-Scale InputJESD204B Interface:Subclass 1 Support1 Lane per ADC Up to 10 GbpsDedicated SYNC Pin for Pair of ChannelsSupport for Multi-Chip Synchronization72-Pin VQFN Package (10 mm × 10 mm)Power Dissipation: 625 mW/ChSpectral Performance (Burst Mode, High Resolution):fIN= 190 MHz IF at –1 dBFS:SNR: 69 dBFSNSD: –153 dBFS/HzSFDR: 86 dBc (HD2, HD3), 95 dBFS (Non HD2, HD3)fIN= 370 MHz IF at –3 dBFS:SNR: 68.5 dBFSNSD: –152.5 dBFS/HzSFDR: 80 dBc (HD2, HD3), 86 dBFS (Non HD2, HD3)Quad Channel14-Bit ResolutionMaximum Sampling Rate: 1 GSPSMaximum Output Sample Rate: 500 MSPSAnalog Input Buffer With High-Impedance InputInput 3-dB Bandwidth: 1 GHzOutput Options:Rx: Decimate-by-2 and -4 Options With Low-Pass Filter200-MHz Complex Bandwidth or 100-MHz Real Bandwidth SupportDPD FB: 2x Decimation With 14-Bit Burst Mode Output1.1-VPPDifferential Full-Scale InputJESD204B Interface:Subclass 1 Support1 Lane per ADC Up to 10 GbpsDedicated SYNC Pin for Pair of ChannelsSupport for Multi-Chip Synchronization72-Pin VQFN Package (10 mm × 10 mm)Power Dissipation: 625 mW/ChSpectral Performance (Burst Mode, High Resolution):fIN= 190 MHz IF at –1 dBFS:SNR: 69 dBFSNSD: –153 dBFS/HzSFDR: 86 dBc (HD2, HD3), 95 dBFS (Non HD2, HD3)fIN= 370 MHz IF at –3 dBFS:SNR: 68.5 dBFSNSD: –152.5 dBFS/HzSFDR: 80 dBc (HD2, HD3), 86 dBFS (Non HD2, HD3)

Description

The ADS58J64 is a low-power, wide-bandwidth, 14-bit, 1-GSPS, quad-channel, telecom receiver device. The ADS58J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS58J64 also supports a 14-bit, 500-MSPS output in burst mode, making the device suitable for a digital pre-distortion (DPD) observation receiver. The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADS58J64 is a low-power, wide-bandwidth, 14-bit, 1-GSPS, quad-channel, telecom receiver device. The ADS58J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS58J64 also supports a 14-bit, 500-MSPS output in burst mode, making the device suitable for a digital pre-distortion (DPD) observation receiver. The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.