LMK04714-Q1 Series
Automotive, ultra low-noise 3.2-GHz, JESD204B and JESD204C dual-loop clock jitter cleaner
Manufacturer: Texas Instruments
Catalog
Automotive, ultra low-noise 3.2-GHz, JESD204B and JESD204C dual-loop clock jitter cleaner
Key Features
• AEC-Q100 Grade 1: –40°C to 125°CMaximum clock output frequency: 3255 MHzMulti-mode: dual PLL, single PLL, and clock distribution6-GHz external VCO or distribution inputUltra-low noise, at 2500 MHz:54-fs RMS jitter (12 kHz to 20 MHz)64-fs RMS jitter (100 Hz to 20 MHz)–157.6-dBc/Hz noise floorUltra-low noise, at 3200 MHz:61-fs RMS jitter (12 kHz to 20 MHz)67-fs RMS jitter (100 Hz to 100 MHz)–156.5-dBc/Hz noise floorPLL2PLL FOM of –230 dBc/HzPLL 1/f of –128 dBc/HzPhase detector rate up to 320 MHzTwo integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHzUp to 14 differential device clocksCML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputsUp to 1 buffered VCXO/XO outputLVPECL, LVDS, 2xLVCMOS programmable1-1023 CLKOUT integer divider1-8191 SYSREF integer divider25-ps step analog delay for SYSREF clocksDigital delay and dynamic digital delay for device clocks and SYSREFHoldover mode with PLL10-delay with PLL1 or PLL2High ReliabilityControlled BaselineOne Assembly/Test SiteOne Fabrication SiteExtended Product Life CycleExtended Product-Change NotificationProduct TraceabilityAEC-Q100 Grade 1: –40°C to 125°CMaximum clock output frequency: 3255 MHzMulti-mode: dual PLL, single PLL, and clock distribution6-GHz external VCO or distribution inputUltra-low noise, at 2500 MHz:54-fs RMS jitter (12 kHz to 20 MHz)64-fs RMS jitter (100 Hz to 20 MHz)–157.6-dBc/Hz noise floorUltra-low noise, at 3200 MHz:61-fs RMS jitter (12 kHz to 20 MHz)67-fs RMS jitter (100 Hz to 100 MHz)–156.5-dBc/Hz noise floorPLL2PLL FOM of –230 dBc/HzPLL 1/f of –128 dBc/HzPhase detector rate up to 320 MHzTwo integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHzUp to 14 differential device clocksCML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputsUp to 1 buffered VCXO/XO outputLVPECL, LVDS, 2xLVCMOS programmable1-1023 CLKOUT integer divider1-8191 SYSREF integer divider25-ps step analog delay for SYSREF clocksDigital delay and dynamic digital delay for device clocks and SYSREFHoldover mode with PLL10-delay with PLL1 or PLL2High ReliabilityControlled BaselineOne Assembly/Test SiteOne Fabrication SiteExtended Product Life CycleExtended Product-Change NotificationProduct Traceability
Description
AI
The LMK04714-Q1 is a high performance clock conditioner with JEDEC JESD204B/C support for space applications.
The 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B/C applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.
This device can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.
The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows to provide flexible high performance clocking trees.
The LMK04714-Q1 is a high performance clock conditioner with JEDEC JESD204B/C support for space applications.
The 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B/C applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.
This device can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.
The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows to provide flexible high performance clocking trees.
