ADSP-21573 Series
Dual-core SHARC+ DSP (w/768KB L1), 1MB Shared L2, DDR, 400-cspBGA
Manufacturer: Analog Devices
Catalog
Dual-core SHARC+ DSP (w/768KB L1), 1MB Shared L2, DDR, 400-cspBGA
Key Features
• Dual-enhanced SHARC+ high performance floating-point coresUp to 500 MHz per SHARC+ coreUp to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache)32-bit, 40-bit, and 64-bit floating-point support32-bit fixed pointByte, short word, word, long word addressed
• Up to 500 MHz per SHARC+ core
• Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache)
• 32-bit, 40-bit, and 64-bit floating-point support
• 32-bit fixed point
• Byte, short word, word, long word addressed
• arm®Cortex-A5 core500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle32 kB L1 instruction cache with parity/32 kB L1 data cache with parity256 kB L2 cache with parity
• 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
• 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity
• 256 kB L2 cache with parity
• Powerful DMA system
• On-chip memory protection
• Integrated safety features
• 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant
• Low system power across automotive temperature range
• Large on-chip L2 SRAM with ECC protection, up to 1 MB
• One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices
• Security and ProtectionCryptographic hardware acceleratorsFast secure boot with IP protectionSupport for arm®TrustZone
• Cryptographic hardware accelerators
• Fast secure boot with IP protection
• Support for arm®TrustZone
• AcceleratorsFIR, IIR offload engines
• FIR, IIR offload engines
• Qualified for automotive applications
Description
AI
The ADSP-SC57x/ADSP-2157x processors are members of the SHARC®family of products. The ADSP-SC57x processor is based on the SHARC+®dual-core and the arm®Cortex®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.By integrating a set of industry leading system peripherals and memory, the arm®Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.
