DS90CR217 Series
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Transmitter - 85 MHz
Manufacturer: Texas Instruments
Catalog
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Transmitter - 85 MHz
Key Features
• 20 to 85 MHz Shift Clock Support50% Duty Cycle on Receiver Output ClockBest-in-Class Set & Hold Times on TxINPUTsLow Power Consumption±1V Common-Mode Range (Around +1.2V)Narrow Bus Reduces Cable Size and CostUp to 1.785 Gbps ThroughputUp to 223 Mbytes/sec Bandwidth345 mV (typ) Swing LVDS Devices for Low EMIPLL Requires No External ComponentsRising Edge Data StrobeCompatible with TIA/EIA-644 LVDS StandardLow Profile 48-Lead TSSOP PackageAll trademarks are the property of their respective owners.20 to 85 MHz Shift Clock Support50% Duty Cycle on Receiver Output ClockBest-in-Class Set & Hold Times on TxINPUTsLow Power Consumption±1V Common-Mode Range (Around +1.2V)Narrow Bus Reduces Cable Size and CostUp to 1.785 Gbps ThroughputUp to 223 Mbytes/sec Bandwidth345 mV (typ) Swing LVDS Devices for Low EMIPLL Requires No External ComponentsRising Edge Data StrobeCompatible with TIA/EIA-644 LVDS StandardLow Profile 48-Lead TSSOP PackageAll trademarks are the property of their respective owners.
Description
AI
The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 1.785 Gbit/s (223 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 1.785 Gbit/s (223 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
