ADC34RF55 Series
Quad-channel, 14-bit, 3-GSPS, low noise spectral density (NSD), RF-sampling ADC
Manufacturer: Texas Instruments
Catalog
Quad-channel, 14-bit, 3-GSPS, low noise spectral density (NSD), RF-sampling ADC
Key Features
• 14-Bit, quad channel 3-GSPS ADCMax output rate: 1.5-GSPSNoise spectral density:-156 dBFS/Hz without averaging-158 dBFS/Hz with 2x averagingSingle core (non-interleaved) ADC architectureAperture jitter: 50 fsLow close-in residual phase noise:-127 dBc/Hz at 10 kHz offsetSpectral performance (f IN = 0.9 GHz, -4 dBFS):2x internal averagingSNR: 62.3 dBFSSFDR HD2,3: 63 dBcSFDR worst spur: 85 dBFSSpectral performance (f IN = 1.8 GHz, -4 dBFS):2x internal averagingSNR: 63 dBFSSFDR HD2,3: 68 dBcSFDR worst spur: 86 dBFSInput full scale: 1.1, 1.35 Vpp (2, 3.5 dBm)Code error rate (CER): 10 -15Full power input bandwidth (-3 dB): 2.75 GHzJESD204B serial data interfaceMaximum lane rate: 13 GbpsSupports subclass 1 deterministic latencyDigital down-convertersUp to two DDC per ADC channelComplex output: 4x to 128x decimation48-bit NCO phase coherent frequency hoppingFast frequency hopping: < 1 µsPower consumption: 1.2 W/channelPower supplies: 1.8 V, 1.2 V14-Bit, quad channel 3-GSPS ADCMax output rate: 1.5-GSPSNoise spectral density:-156 dBFS/Hz without averaging-158 dBFS/Hz with 2x averagingSingle core (non-interleaved) ADC architectureAperture jitter: 50 fsLow close-in residual phase noise:-127 dBc/Hz at 10 kHz offsetSpectral performance (f IN = 0.9 GHz, -4 dBFS):2x internal averagingSNR: 62.3 dBFSSFDR HD2,3: 63 dBcSFDR worst spur: 85 dBFSSpectral performance (f IN = 1.8 GHz, -4 dBFS):2x internal averagingSNR: 63 dBFSSFDR HD2,3: 68 dBcSFDR worst spur: 86 dBFSInput full scale: 1.1, 1.35 Vpp (2, 3.5 dBm)Code error rate (CER): 10 -15Full power input bandwidth (-3 dB): 2.75 GHzJESD204B serial data interfaceMaximum lane rate: 13 GbpsSupports subclass 1 deterministic latencyDigital down-convertersUp to two DDC per ADC channelComplex output: 4x to 128x decimation48-bit NCO phase coherent frequency hoppingFast frequency hopping: < 1 µsPower consumption: 1.2 W/channelPower supplies: 1.8 V, 1.2 V
Description
AI
The ADC34RF55 is a single core 14-bit, 3-GSPS, quad channel analog to digital converters (ADC) that support RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR), and delivers a noise spectral density of -156 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -158 dBFS/Hz.
Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.
The devices supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13Gbps. There are only 2 serdes lanes per ADC channel. Therefore, in bypass mode, the maximum output data rate supported is 1.5GSPS. When using faster ADC sampling rates on chip, decimation is required.
The power efficient ADC architecture consumes 1.2W/ch and provides power scaling with lower sampling rates.
The ADC34RF55 is a single core 14-bit, 3-GSPS, quad channel analog to digital converters (ADC) that support RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR), and delivers a noise spectral density of -156 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -158 dBFS/Hz.
Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.
The devices supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13Gbps. There are only 2 serdes lanes per ADC channel. Therefore, in bypass mode, the maximum output data rate supported is 1.5GSPS. When using faster ADC sampling rates on chip, decimation is required.
The power efficient ADC architecture consumes 1.2W/ch and provides power scaling with lower sampling rates.
