CD54AC109 Series

Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset

Catalog

Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset

Part	Supplier Device Package	Max Propagation Delay @ V, Max CL	Output Type	Mounting Type	Function	Current - Output High, Low	Number of Bits per Element	Type	Number of Elements	Operating Temperature [Max]	Operating Temperature [Min]	Clock Frequency	Trigger Type	Current - Quiescent (Iq)	Package / Case	Package / Case	Input Capacitance	Voltage - Supply [Max]	Voltage - Supply [Min]
Texas Instruments CD54AC109F3A	16-CDIP	10.3 ns	Complementary	Through Hole	Reset Set(Preset)	24 mA	1	JK Type	2	125 °C	-55 °C	100 MHz	Positive Edge	4 çA	0.3 in 7.62 mm	16-CDIP	10 pF	5.5 V	1.5 V

Catalog

Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset

Key Features

• AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltageSpeed of bipolar F, AS, and S, with significantly reduced power consumptionBalanced propagation delays±24mA output drive currentFanout to 15 F devicesSCR-latchup-resistant CMOS process and circuit designExceeds 2kV ESD protection per MIL-STD-883, method 3015AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltageSpeed of bipolar F, AS, and S, with significantly reduced power consumptionBalanced propagation delays±24mA output drive currentFanout to 15 F devicesSCR-latchup-resistant CMOS process and circuit designExceeds 2kV ESD protection per MIL-STD-883, method 3015

Description

The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications. The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.