ADS54J64 Series

Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling Analog-to-Digital Converter (ADC)

Catalog

Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling Analog-to-Digital Converter (ADC)

Part	Supplier Device Package	Sampling Rate (Per Second)	Number of Bits	Number of Inputs	Features	Configuration	Number of A/D Converters	Voltage - Supply, Analog [Max]	Voltage - Supply, Analog [Min]	Architecture	Ratio - S/H:ADC	Mounting Type	Data Interface	Package / Case	Reference Type	Input Type	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]
Texas Instruments ADS54J64IRMPT	72-VQFN (10x10)	1 G	14	4	Simultaneous Sampling	S/H-ADC	4	1.2 V 2 V	1.1 V 1.8 V	Pipelined	1:1	Surface Mount	JESD204B	72-VFQFN Exposed Pad	Internal	Differential	1.2 V	1.1 V
Texas Instruments ADS54J64IRMP	72-VQFN (10x10)	1 G	14	4	Simultaneous Sampling	S/H-ADC	4	1.2 V 2 V	1.1 V 1.8 V	Pipelined	1:1	Surface Mount	JESD204B	72-VFQFN Exposed Pad	Internal	Differential	1.2 V	1.1 V

Catalog

Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling Analog-to-Digital Converter (ADC)

Key Features

• Quad Channel, 14-Bit ResolutionMaximum Sampling Rate: 1 GSPSMaximum Output Sample Rate: 500 MSPSHigh-Impedance Analog Input BufferAnalog Input Bandwidth (–3 dB): 1 GHzOutput Options:Digital Down Conversion (DDC) Using 16-Bit NCODDC Bypass With Full Rate Output Up to 500 MSPSDifferential Full-Scale Input: 1.1 VPPJESD204B Interface:Subclass 1 Support1 Lane per ADC Up to 10 GbpsDedicated SYNC Pin for Pair of ChannelsSupport for Multi-Chip SynchronizationSpectral Performance:fIN= 190-MHz IF at –1 dBFS:SNR: 69 dBFSNSD: –153 dBFS/HzSFDR: 86 dBc (HD2, HD3),95 dBFS (Non HD2, HD3)fIN= 370-MHz IF at –3 dBFS:SNR: 68.5 dBFSNSD: –152.5 dBFS/HzSFDR: 80 dBc (HD2, HD3),86 dBFS (Non HD2, HD3)72-Pin VQFN Package (10 mm × 10 mm)Power Consumption: 625 mW/Ch, 2.5 W TotalPower Supplies: 1.15 V, 1.15 V, 1.9 VQuad Channel, 14-Bit ResolutionMaximum Sampling Rate: 1 GSPSMaximum Output Sample Rate: 500 MSPSHigh-Impedance Analog Input BufferAnalog Input Bandwidth (–3 dB): 1 GHzOutput Options:Digital Down Conversion (DDC) Using 16-Bit NCODDC Bypass With Full Rate Output Up to 500 MSPSDifferential Full-Scale Input: 1.1 VPPJESD204B Interface:Subclass 1 Support1 Lane per ADC Up to 10 GbpsDedicated SYNC Pin for Pair of ChannelsSupport for Multi-Chip SynchronizationSpectral Performance:fIN= 190-MHz IF at –1 dBFS:SNR: 69 dBFSNSD: –153 dBFS/HzSFDR: 86 dBc (HD2, HD3),95 dBFS (Non HD2, HD3)fIN= 370-MHz IF at –3 dBFS:SNR: 68.5 dBFSNSD: –152.5 dBFS/HzSFDR: 80 dBc (HD2, HD3),86 dBFS (Non HD2, HD3)72-Pin VQFN Package (10 mm × 10 mm)Power Consumption: 625 mW/Ch, 2.5 W TotalPower Supplies: 1.15 V, 1.15 V, 1.9 V

Description

The ADS54J64 device is a quad-channel, 14-bit,1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode. A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADS54J64 device is a quad-channel, 14-bit,1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode. A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.