ADS54J54 Series
Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Catalog
Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter (ADC)
Key Features
• 4 Channel, 14-Bit 500 MSPS ADCAnalog input buffer with high impedance inputFlexible input clock buffer with divide by 1/2/41.25 VPPDifferential full-scale inputJESD204B Serial interfaceSubclass 1 compliant up to 5 Gbps1 Lane Per ADC up to 250 Msps2 Lanes Per ADC up to 500 Msps64-Pin QFN Package (9 mm x 9 mm)Key specifications:Power dissipation: 875 mW/chInput bandwidth (3 dB): 900 MHzAperture jitter: 98 fs rmsChannel isolation: 85 dBPerformance at ƒin= 170 MHz at 1.25 VPP,1lane 2x Decimation –1 dBFSSNR: 67.2 dBFSSFDR: 85 dBc HD2,3; 95 dBFS non-HD2,3Performance at ƒin= 370 MHz at 1.25 VPP,2lane no Decimation –1 dBFSSNR: 64.7 dBFSSFDR: 75 dBc HD2,3; 83 dBFS non-HD2,34 Channel, 14-Bit 500 MSPS ADCAnalog input buffer with high impedance inputFlexible input clock buffer with divide by 1/2/41.25 VPPDifferential full-scale inputJESD204B Serial interfaceSubclass 1 compliant up to 5 Gbps1 Lane Per ADC up to 250 Msps2 Lanes Per ADC up to 500 Msps64-Pin QFN Package (9 mm x 9 mm)Key specifications:Power dissipation: 875 mW/chInput bandwidth (3 dB): 900 MHzAperture jitter: 98 fs rmsChannel isolation: 85 dBPerformance at ƒin= 170 MHz at 1.25 VPP,1lane 2x Decimation –1 dBFSSNR: 67.2 dBFSSFDR: 85 dBc HD2,3; 95 dBFS non-HD2,3Performance at ƒin= 370 MHz at 1.25 VPP,2lane no Decimation –1 dBFSSNR: 64.7 dBFSSFDR: 75 dBc HD2,3; 83 dBFS non-HD2,3
Description
AI
The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel analog-to-digital converter (ADC). It supports the JESD204B serial interface with data rates up to 5 Gbps supporting 1 or 2 lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. Optional 2x Decimation Filter provides high-pass or low-pass filter modes.
The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel analog-to-digital converter (ADC). It supports the JESD204B serial interface with data rates up to 5 Gbps supporting 1 or 2 lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. Optional 2x Decimation Filter provides high-pass or low-pass filter modes.
