Catalog
18-bit bus LVDS serializer/deserializer - 15-66 MHz
Key Features
• 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down PinsHot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated ClocksLine and Local Loopback ModesRobust BLVDS Serial Transmission Across Backplanes and Cables for Low EMINo External Coding RequiredInternal PLL, No External PLL Components RequiredSingle +3.3V Power SupplyLow Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern±100 mV Receiver Input ThresholdLoss of Lock Detection and Reporting PinIndustrial −40 to +85°C Temperature Range>2.0kV HBM ESDCompact, Standard 80-Pin LQFP PackageAll trademarks are the property of their respective owners.15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down PinsHot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated ClocksLine and Local Loopback ModesRobust BLVDS Serial Transmission Across Backplanes and Cables for Low EMINo External Coding RequiredInternal PLL, No External PLL Components RequiredSingle +3.3V Power SupplyLow Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern±100 mV Receiver Input ThresholdLoss of Lock Detection and Reporting PinIndustrial −40 to +85°C Temperature Range>2.0kV HBM ESDCompact, Standard 80-Pin LQFP PackageAll trademarks are the property of their respective owners.
Description
AI
The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.
The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.
The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.
The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.
