ADS54J66 Series
Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Catalog
Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter (ADC)
Key Features
• Quad channel14-Bit resolutionMaximum clock rate: 500 MSPSInput bandwidth (3 dB): 900 MHzOn-chip ditherAnalog Input buffer with high-impedance inputOutput options:Rx: decimate-by-2 and -4 options with Low-Pass lFilter200-MHz Complex bandwidth or 100-MHz real bandwidth supportDPD FB: 500 MSPS1.9-VPPDifferential full-scale inputJESD204B interface:Subclass 1 support1 Lane per ADC Up to 10 GbpsDedicated SYNC pin for pair of channelsSupport for multi-chip synchronization72-Pin VQFN package (10 mm × 10 mm)Key specifications:Power dissipation: 675 mW/chSpectral performance (un-decimated)fIN= 190 MHz IF at –1 dBFS:SNR: 69.5 dBFSNSD: –153.5 dBFS/HzSFDR: 86 dBc (HD2, HD3), 93 dBFS (Non HD2, HD3)fIN= 370 MHz IF at –3 dBFS:SNR: 68.5 dBFSNSD: –152.5 dBFS/HzSFDR: 81 dBc (HD2, HD3), 86 dBFS (Non HD2, HD3)Quad channel14-Bit resolutionMaximum clock rate: 500 MSPSInput bandwidth (3 dB): 900 MHzOn-chip ditherAnalog Input buffer with high-impedance inputOutput options:Rx: decimate-by-2 and -4 options with Low-Pass lFilter200-MHz Complex bandwidth or 100-MHz real bandwidth supportDPD FB: 500 MSPS1.9-VPPDifferential full-scale inputJESD204B interface:Subclass 1 support1 Lane per ADC Up to 10 GbpsDedicated SYNC pin for pair of channelsSupport for multi-chip synchronization72-Pin VQFN package (10 mm × 10 mm)Key specifications:Power dissipation: 675 mW/chSpectral performance (un-decimated)fIN= 190 MHz IF at –1 dBFS:SNR: 69.5 dBFSNSD: –153.5 dBFS/HzSFDR: 86 dBc (HD2, HD3), 93 dBFS (Non HD2, HD3)fIN= 370 MHz IF at –3 dBFS:SNR: 68.5 dBFSNSD: –152.5 dBFS/HzSFDR: 81 dBc (HD2, HD3), 86 dBFS (Non HD2, HD3)
Description
AI
The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.
The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.
The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.
The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.
